参数资料
型号: ISL6719ARZ-T
厂商: Intersil
文件页数: 7/9页
文件大小: 0K
描述: IC REG LDO ADJ .1A 9-DFN
标准包装: 6,000
稳压器拓扑结构: 正,可调式
输出电压: 1.5 V ~ 20 V
输入电压: 18 V ~ 80 V
稳压器数量: 1
电流 - 输出: 100mA(最小值)
电流 - 限制(最小): 100mA
工作温度: -40°C ~ 105°C
安装类型: 表面贴装
封装/外壳: 9-VFDFN 裸露焊盘
供应商设备封装: 9-DFN-EP(3x3)
包装: 带卷 (TR)
ISL6719
AUXIN
AUXIN is the auxiliary input of the ISL6719, accepting bias
voltage whenever the input source voltage, VPWR, is above
1
VPWR
GND 9
its undervoltage lockout (UVLO) threshold. VSW selects
ENABLE_N 8
AUXIN as its source when it is capable supporting the load
on VSW. Otherwise VPWR is selected.
2
ENABLE
AUXIN
7
AUXIN can accept voltages up to 40V maximum. Voltages in
VSW
3
VSW COMPB
6
excess of 40V, including transients, will cause permanent
damage to the device. Care should be taken when
connecting external sources through very long traces or lead
wires. The lead inductance may cause unexpected
C2
R1
4
COMPA 5
VSW_FB
transients in excess of the device’s ratings. In such
circumstances it is recommended that a small resistor be
placed between AUXIN and the external source to dampen
the transient. A value of 10 Ω to 100 Ω is usually sufficient.
VSW
VSW is the switched output and may be turned on and off
using the ENABLE or ENABLE_N pins. VSW is adjustable
1.0 μ F
R2
C3
220pF
from 1.5V to 20V, but must always be at least 6.2V lower
than VPWR at rated load. Additionally, VSW must be at least
3.0V lower than AUXIN for it to function as the source for
VSW. As the differential voltage between AUXIN and VSW
drops below 3.0V, the input current will shift from AUXIN to
VPWR. The voltage headroom required is load dependent.
See Figures 1 and 2. VSW preferentially uses AUXIN as its
input source, but if AUXIN is unable to supply adequate
voltage, VPWR is selected as the alternate input source.
VSW is capable of delivering up to 100mA continuously,
depending on power dissipation and the thermal
environment in which the device is placed.
The output voltage is adjusted using the VSW_FB input.
VSW is set with a resistor divider from VSW to ground with
the central node connected to VSW_FB. Refer to Figure 5.
FIGURE 5. VSW ADJUSTMENT AND COMPENSATION
TRACE 1: VSW
TRACE 2: I VSW
VSW = V REF --------------------- – I BIAS R 1
R
R 1 + R 2
2
V
(EQ. 1)
Referring to Equation 1, V REF is nominally 1.5V and I BIAS
has a maximum value of 1.5μA. The error introduced by the
VSW_FB bias current can be minimized by making the
product of R 1 x I BIAS small, relative to the magnitude of the
desired output voltage. For example, setting R 1 x I BIAS
equal to 0.5% of VSW yields a value for R 1 equal to 3.33 x
VSW (k Ω ).
VSW requires an external compensation capacitor to remain
stable across the output adjustment range, output
capacitance and loading. A value of 220pF between COMPA
and COMPB is recommended for all operating conditions
with a nominal load capacitance of 1.0μF (0.47μF to 1.5μF).
VSW requires a minimum load of 3mA.
7
FIGURE 6. VSW TRANSIENT RESPONSE, 10mA TO 100mA
STEP, VPWR = 18V, AUXIN = 15V, VSW = 12V
Figure 6 depicts the transient response of VSW during a
10mA to 100mA step load when AUXIN is set to 15V and
VPWR is set to 18V.
VPWR
VPWR provides the source voltage for the IC and load until
AUXIN is back biased. VSW is disabled and the IC operates
in a standby (low power consumption) mode when UVLO is
active.
FN6555.1
October 1, 2007
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