参数资料
| 型号： | ISL6719ARZ-T |
| 厂商： | Intersil |
| 文件页数： | 9/9页 |
| 文件大小： | 0K |
| 描述： | IC REG LDO ADJ .1A 9-DFN |
| 标准包装： | 6,000 |
| 稳压器拓扑结构： | 正，可调式 |
| 输出电压： | 1.5 V ~ 20 V |
| 输入电压： | 18 V ~ 80 V |
| 稳压器数量： | 1 |
| 电流 - 输出： | 100mA（最小值） |
| 电流 - 限制（最小）： | 100mA |
| 工作温度： | -40°C ~ 105°C |
| 安装类型： | 表面贴装 |
| 封装/外壳： | 9-VFDFN 裸露焊盘 |
| 供应商设备封装： | 9-DFN-EP（3x3） |
| 包装： | 带卷 (TR) |
ISL6719
Dual Flat No-Lead Plastic Package (DFN)
2X
0.15 C A
L9.3x3
9 LEAD DUAL FLAT NO-LEAD PLASTIC PACKAGE
A
D
2X
MILLIMETERS
E
0.15 C B
SYMBOL
A
A1
A3
MIN
0.80
-
NOMINAL
0.90
-
0.20 REF
MAX
1.00
0.05
NOTES
-
-
-
5
INDEX
AREA
b
D
0.20
0.25
3.00 BSC
0.30
4, 7
-
TOP VIEW
B
D2
1.85
2.00
2.10
6, 7
E
3.00 BSC
-
A
//
0.10 C
0.08 C
E2
e
k
0.80
0.60
0.95
0.50 BSC
-
1.05
-
6, 7
-
-
C
SEATING
SIDE VIEW
A3
L
0.25
0.35
0.45
7
PLANE
N
9
2
(DATUM B)
5
INDEX
AREA
1
D2
D2/2
2
6
7
NX k
Rev. 0 3/06
NOTES:
1. Dimensioning and tolerancing conform to ASME Y14.5-1994.
2. N is the number of terminals.
3. All dimensions are in millimeters. Angles are in degrees.
4. Dimension b applies to the metallized terminal and is measured
(DATUM A)
between 0.15mm and 0.30mm from the terminal tip.
E2/2
E2
5. The configuration of the pin #1 identifier is optional, but must be
located within the zone indicated. The pin #1 identifier may be
either a mold or mark feature.
NX L
N
N-1
NX b
6. Dimensions D2 and E2 are for the exposed pads which provide
improved electrical and thermal performance.
7
e
(Nd-1)Xe
REF.
4
0.10 M C A B
7. Nominal dimensions are provided to assist with PCB Land
Pattern Design efforts, see Intersil Technical Brief TB389.
8. COMPLIANT TO JEDEC MO-229-WEED-3 except for
BOTTOM VIEW
CL
dimensions E2 & D2.
NX (b)
4
(A1)
8 L
SECTION "C-C"
C C
e
TERMINAL TIP
FOR ODD TERMINAL/SIDE
All Intersil U.S. products are manufactured, assembled and tested utilizing ISO9000 quality systems.
Intersil Corporation’s quality certifications can be viewed at www.intersil.com/design/quality
Intersil products are sold by description only. Intersil Corporation reserves the right to make changes in circuit design, software and/or specifications at any time without
notice. Accordingly, the reader is cautioned to verify that data sheets are current before placing orders. Information furnished by Intersil is believed to be accurate and
reliable. However, no responsibility is assumed by Intersil or its subsidiaries for its use; nor for any infringements of patents or other rights of third parties which may result
from its use. No license is granted by implication or otherwise under any patent or patent rights of Intersil or its subsidiaries.
For information regarding Intersil Corporation and its products, see www.intersil.com
9
FN6555.1
October 1, 2007
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