参数资料
| 型号： | ISL6720AARZ |
| 厂商： | Intersil |
| 文件页数： | 7/11页 |
| 文件大小： | 0K |
| 描述： | IC REG LDO 5V/ADJ 11-DFN |
| 标准包装： | 75 |
| 稳压器拓扑结构： | 正，固定式和可调式 |
| 输出电压： | 5V，0 V ~ 20 V，0 V ~ 15 V |
| 输入电压： | 18 V ~ 80 V |
| 稳压器数量： | 3 |
| 电流 - 输出： | 25mA（最小），125mA（最小），50mA（最小） |
| 电流 - 限制（最小）： | 30mA，225mA，80mA |
| 工作温度： | -40°C ~ 105°C |
| 安装类型： | 表面贴装 |
| 封装/外壳： | 11-VFDFN 裸露焊盘 |
| 供应商设备封装： | 11-DFN（4x4） |
| 包装： | 管件 |
ISL6720A
Typical Performance Curves
3.5
3.3
3.5
3.3
3.1
2.9
VADJ = 15V
3.1
2.9
2.7
2.7
VPWR = 48V
2.5
2.5 VPWR = 20V
2.3
2.1
1.9
1.7
VADJ = 10V
VADJ = 20V
2.3
2.1
1.9
1.7
VPWR = 80V
1.5
0
10
20
30
40
50
60
70
80
90
100
1.5
0
10
20
30
40
50
60
70
80
90
100
VIO LOAD (mA)
FIGURE 1. VADJ - VIO vs I VIO @ VPWR = 25V, +25°C
1.001
1.000
VIO LOAD (mA)
FIGURE 2. VADJ - VIO vs I VIO @ VADJ = 15V, +25°C
1.002
VSW = 5.0V
1.001
VSW = 20V
0.999
0.998
1.000
0.999
VSW = 3.3V
VSW = 12V
0.997
-40
-25
-10
5
20
35
50
65
80
95
110
0.998
-40
-25
-10
5
20
35
50
65
80
95
110
TEMPERATURE (°C)
FIGURE 3. VCONT REGULATION vs TEMPERATURE
Pin Descriptions
VPWR - VPWR is the primary power connection for the IC.
The under voltage lockout (UVLO) feature of VPWR
enables/disables all outputs even if VIO is externally biased.
To optimize noise immunity, bypass VPWR to GND with a
ceramic capacitor as close to the VPWR and GND pins as
possible.
VCONT - A 25mA continuous output that derives its source
voltage from either VIO (when enabled and sufficient) or
VPWR (when VIO is not available). VCONT sequences on
before VIO and VSW by approximately 250 μ s.
The over-temperature protection feature protects VCONT at
a higher temperature than VIO and VSW. This ensures VIO
and VSW shutdown at a lower temperature and allows
VCONT to remain on.
VCOMP - A 1000pF compensating capacitor is placed
between VCOMP and VCONT to stabilize the control loop.
This value may vary depending on the output load and
capacitance applied between VCONT and GND.
7
TEMPERATURE (°C)
FIGURE 4. VSW REGULATION vs TEMPERATURE
VIO - This is the unswitched low voltage output supply. It
may be used as is, or may be back-biased by an auxiliary
power source such as a transformer winding. VIO should be
bypassed to GND with a 0.1 μ F capacitor. Although a
minimum capacitance is not required, it does provide the
source voltage bypass for VSW and VCONT when VIO is
capable of supporting those outputs. Smaller values of
capacitance will result in larger disturbances during load
transients. Its output is adjustable from 0V to 20.0V using a
reference on VADJ, such as a zener diode and bias resistor.
VIO may be soft-started with a capacitance to ground from
VADJ.
VADJ - The feedback adjustment pin for VIO. An external
reference on VADJ sets the voltage on VIO. The reference
may be a resistor/zener diode combination from VPWR.
VADJ has a discharge device that activates momentarily
during power-up and power-down sequences to allow VIO to
be soft started.
GND - Signal and power ground connections for this device.
FN6487.1
August 23, 2007
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