参数资料
| 型号： | ISL6720AARZ |
| 厂商： | Intersil |
| 文件页数： | 8/11页 |
| 文件大小： | 0K |
| 描述： | IC REG LDO 5V/ADJ 11-DFN |
| 标准包装： | 75 |
| 稳压器拓扑结构： | 正，固定式和可调式 |
| 输出电压： | 5V，0 V ~ 20 V，0 V ~ 15 V |
| 输入电压： | 18 V ~ 80 V |
| 稳压器数量： | 3 |
| 电流 - 输出： | 25mA（最小），125mA（最小），50mA（最小） |
| 电流 - 限制（最小）： | 30mA，225mA，80mA |
| 工作温度： | -40°C ~ 105°C |
| 安装类型： | 表面贴装 |
| 封装/外壳： | 11-VFDFN 裸露焊盘 |
| 供应商设备封装： | 11-DFN（4x4） |
| 包装： | 管件 |
ISL6720A
VSW - This is the switched regulated low voltage output
supply derived from VIO. Bypass to GND with a 1.0 μ F
capacitor. Its output is adjustable from 0V to 15.0V using an
appropriate divider from VCONT to VADJ and GND. VSW is
nominally 7 x VSWADJ. Protection circuitry prevents the
output from exceeding 23V in the event of a fault on
VSWADJ (short high). The minimum output current
capability is 50mA with transient capability to > 80mA. VSW
may be soft-started by placing a capacitor from VSWADJ to
GND.
ENABLE - The positive logic on/off control input that
on VIO gradually transfers from the VIO regulator to external
back-bias source. Depending on load, the back-bias voltage
may have to exceed the VIO setpoint by as much as 3V
before the VIO regulator is off.
The output voltage of VIO is set by applying a reference
voltage to VADJ. The reference voltage may be set by using
a resistor and zener diode combination from the VPWR
input. VIO ranges from 0.5V to 4.5V below the voltage
applied to VADJ depending on the load on VIO. VIO can
source more than 125mA for short durations, limited only by
the device power dissipation and the thermal constraints of
the application.
controls the VSW output. A logic high enables VSW.
VIO = VADJ – V OFFSET
V
(EQ. 1)
VSWCOMP - A 220pF compensating capacitor is placed
between VSWCOMP and VSW to stabilize the control loop.
This value may vary depending on the output load and
capacitance applied between VSW and GND.
VSWADJ - The feedback adjustment pin for VSW. A divider
where V OFFSET ranges from 0.5V to 4.5V.
from VCONT to GND sets the output voltage for VSW.
VIN
1
VPWR
VIO 11
VSWADJ has a node discharge device that activates
momentarily at power-up, when disabled (ENABLE low), and
N/C 10
during power-down sequences. VSW is nominally
2
VCONT VADJ
9
7 x VSWADJ.
3
VCOMP
VSW
8
Functional Description
4
GND VSWCOMP
7
Features
5
VSWADJ
ENABLE
6
The control circuitry used in Telecom/Datacom DC/DC
converters often requires an operating bias voltage
significantly lower than the source voltage available to the
converter. Many applications use a discrete linear regulator
from the input source to create the bias supply. Often an
auxiliary winding from the power transformer is used to
supplement or replace the linear supply once the converter
is operating. The auxiliary winding bias voltage may require
regulation, as well, to minimize the voltage variation inherent
in unregulated transformer winding outputs. When
implemented discretely, this circuitry occupies significant
PWB area, a considerable problem in today’s high density
converters.
The ISL6720A triple linear regulator simplifies the start-up
and operating bias circuitry needed in Telecom and Datacom
DC/DC converters by integrating these functions, and more,
in a small 4mmx4mm DFN package.
VIO
VIO is the primary output of the ISL6720A, providing bias
voltage whenever the input source voltage, VPWR, is above
its under voltage lockout (UVLO) threshold. VIO, which is an
abbreviation for “voltage input/output”, is adjustable from
0.5V to 20V using the VADJ input, and may be back-biased
up to 40V from an external source independent of VPWR.
The back-bias voltage must be higher than the VIO setpoint
to disable the internal VIO regulator. The transition from
internal VIO to external VIO is not abrupt. As the back-bias
voltage increases above the VIO setpoint, the load current
8
FIGURE 5. SETPOINT ADJUSTMENT FOR VIO
VIO may be soft-started using the VADJ input. By limiting the
rate of rise of VADJ, the risetime of VIO may be controlled.
Soft-start may be accomplished by placing a capacitor to
ground from VADJ. The capacitor to ground and the resistor
from VPWR determine the RC charging characteristic for the
voltage at VADJ. Since VADJ is pulled low at power-up and
power-down, soft-start always starts from a known state.
The soft-start rate cannot exceed the intrinsic risetime set by
the current limit threshold of the output. As load capacitance
increases, the intrinsic risetime increases. In general,
placing large capacitance values on VIO should be avoided,
particularly if the source voltage applied to VPWR is high.
Having a large load capacitance and high input voltage
results in high power dissipation for a longer duration and
may activate the over-temperature protection before VIO
can be biased externally. Under such conditions, steady
state operation would not be achievable.
If the auxiliary transformer winding used to back-bias VIO
requires a large value of capacitance, it can be isolated from
VIO using a diode as shown in Figure 6.
FN6487.1
August 23, 2007
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| ISL6720AARZ-T | 功能描述:线性稳压器 - 标准 100V LINEAR BIAS SUPPLY 4X4 RoHS:否 制造商:STMicroelectronics 输出类型: 极性: 输出电压:1.8 V 输出电流:150 mA 负载调节: 最大输入电压:5.5 V 线路调整率: 最大工作温度:+ 125 C 安装风格:SMD/SMT 封装 / 箱体:SOT-323-5L |
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