参数资料
| 型号： | ISL6740AIVZA |
| 厂商： | Intersil |
| 文件页数： | 10/14页 |
| 文件大小： | 0K |
| 描述： | IC REG CTRLR PWM VM 16-TSSOP |
| 标准包装： | 960 |
| PWM 型： | 电压模式 |
| 输出数： | 1 |
| 频率 - 最大： | 2MHz |
| 占空比： | 100% |
| 电源电压： | 9 V ~ 16 V |
| 降压： | 无 |
| 升压： | 无 |
| 回扫： | 无 |
| 反相： | 无 |
| 倍增器： | 无 |
| 除法器： | 无 |
| Cuk： | 无 |
| 隔离： | 无 |
| 工作温度： | -40°C ~ 105°C |
| 封装/外壳： | 16-TSSOP（0.173"，4.40mm 宽） |
| 包装： | 管件 |
ISL6740A
R TC and C T . The discharge duration is determined by R TD and
C T .
Soft-Start Operation
Soft-start is controlled using an external capacitor in
t C ≈ 0.5 ? R TC ? C T
S
(EQ. 2)
conjunction with an internal current source. Soft-start reduces
stresses and surge currents during start up.
t SW = t C + t D = -----------
t D ≈ 0.02 ? R TD ? C T
1
F SW
S
S
(EQ. 3)
(EQ. 4)
Upon start up, the soft-start circuitry clamps the error voltage
input (V ERROR pin) indirectly to a value equal to the soft-start
voltage. The soft-start clamp does not actually clamp the error
voltage input as is done in many implementations. Rather the
PWM comparator has two inverting inputs such that the lower
voltage is in control.
where t C and t D are the charge and discharge times,
respectively, t SW is the oscillator free running period, and f is
the oscillator frequency. One output switching cycle requires
two oscillator cycles. The actual times will be slightly longer
than calculated due to internal propagation delays of
approximately 10ns/transition. This delay ads directly to the
switching duration, but also causes overshoot of the timing
capacitor peak and valley voltage thresholds, effectively
increasing the peak-to-peak voltage on the timing capacitor.
Additionally, if very low charge and discharge currents are
used, there will be increased error due to the input impedance
at the C T pin.
The maximum duty cycle, D, and percent deadtime, DT, can be
calculated from:
The output pulse width increases as the soft-start capacitor
voltage increases. This has the effect of increasing the duty
cycle from zero to the regulation pulse width during the soft-
start period. When the soft-start voltage exceeds the error
voltage at the PWM comparator inputs, soft-start is completed.
Soft-start occurs during start-up, after recovery from a Fault
condition or overcurrent/short circuit shutdown. The soft-start
voltage is clamped to 4.5V.
The Fault signal output is high impedance during the soft-start
is present. A pull-up resistor to VREF or a pull-down resistor to
ground should be added to achieve the desired state of Fault
during soft-start.
t C
t SW
D = ----------
DT = 1 – D
(EQ. 5)
(EQ. 6)
Gate Drive
The outputs are capable of sourcing and sinking 0.5A peak
current, but are primarily intended to be used in conjunction
with a MOSFET driver due to the 5V drive level. To limit the
peak current through the IC, an external resistor may be placed
between the totem-pole output of the IC (OUTA or OUTB pin)
Figures 3 and 4 graphically portray the deadtime and oscillator
frequency as function of the timing components.
Implementing Synchronization
The oscillator can be synchronized to an external clock applied
to the SYNC pin or by connecting the SYNC pins of multiple ICs
together. If an external master clock signal is used, the free
running frequency of the oscillator should be ~10% slower
than the desired synchronous frequency. The external master
clock signal should have a pulse width greater than 20ns. The
SYNC circuitry will not respond to an external signal during the
first 60% of the oscillator switching cycle. Self-synchronization
is not recommended for oscillator frequencies above 900kHz.
For higher switching frequencies, an external clock with a
pulse width less than one-half of the oscillator period must be
used.
The SYNC input is edge triggered and its duration does not
affect oscillator operation. However, the deadtime is affected
by the SYNC frequency. A higher frequency signal applied to
the SYNC input will shorten the deadtime. The shortened
deadtime is the result of the timing capacitor charge cycle
being prematurely terminated by the external SYNC pulse.
Consequently, the timing capacitor is not fully charged when
the discharge cycle begins. This effect is only a concern when
an external master clock is used, or if units with different
operating frequencies are paralleled.
10
and the gate of the MOSFET. This small series resistor also
damps any oscillations caused by the resonant tank formed by
the parasitic inductances in the traces of the board and the
device’s input capacitance.
Undervoltage Monitor, Inhibit, and
Feed-Forward
The UV/FF input is used for input source undervoltage lockout
and inhibit functions as well as sensing the input voltage for
feed forward compensation.
If the node voltage falls below 1.00V, a UV shutdown fault
occurs. This may be caused by low source voltage or by
intentional grounding of the pin to disable the outputs. There is
a nominal 10 μ A switched current source used to create
hysteresis. The current source is active only during a UV/Inhibit
fault; otherwise, it is inactive and does not affect the node
voltage. The magnitude of the hysteresis is a function of the
external resistor divider impedance. If the resistor divider
impedance results in too little hysteresis, a series resistor
between the UV pin and the divider may be used to increase
the hysteresis. A soft-start cycle begins when the UV/Inhibit
fault clears.
The voltage hysteresis created by the switched current source
and the external impedance is generally small due to the large
resistor divider ratio required to scale the input voltage down
to the UV threshold level. A small capacitor placed between the
UV input and ground may be required to filter noise out.
FN9195.3
February 9, 2012
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| ISL6740AIVZA-T | 功能描述:IC REG CTRLR PWM VM 16-TSSOP RoHS:是 类别:集成电路 (IC) >> PMIC - 稳压器 - DC DC 切换控制器 系列:- 产品培训模块:Lead (SnPb) Finish for COTS Obsolescence Mitigation Program 标准包装:2,500 系列:- PWM 型:电流模式 输出数:1 频率 - 最大:275kHz 占空比:50% 电源电压:18 V ~ 110 V 降压:无 升压:无 回扫:无 反相:无 倍增器:无 除法器:无 Cuk:无 隔离:是 工作温度:-40°C ~ 85°C 封装/外壳:8-SOIC（0.154"，3.90mm 宽） 包装:带卷 (TR) |
| ISL6740EVAL1 | 功能描述:EVALUATION BOARD 1 ISL6740 RoHS:否 类别:编程器，开发系统 >> 评估板 - DC/DC 与 AC/DC（离线）SMPS 系列:- 产品培训模块:Obsolescence Mitigation Program 标准包装:1 系列:True Shutdown™ 主要目的:DC/DC，步升 输出及类型:1，非隔离 功率 - 输出:- 输出电压:- 电流 - 输出:1A 输入电压:2.5 V ~ 5.5 V 稳压器拓扑结构:升压 频率 - 开关:3MHz 板类型:完全填充 已供物品:板 已用 IC / 零件:MAX8969 |
| ISL6740EVAL2 | 功能描述:EVALUATION BOARD 2 ISL6740 RoHS:否 类别:编程器，开发系统 >> 过时/停产零件编号 系列:- 标准包装:1 系列:- 传感器类型:CMOS 成像，彩色（RGB） 传感范围:WVGA 接口:I²C 灵敏度:60 fps 电源电压:5.7 V ~ 6.3 V 嵌入式:否 已供物品:成像器板 已用 IC / 零件:KAC-00401 相关产品:4H2099-ND - SENSOR IMAGE WVGA COLOR 48-PQFP4H2094-ND - SENSOR IMAGE WVGA MONO 48-PQFP |
| ISL6740EVAL2Z | 功能描述:EVALUATION BOARD 2 ISL6740 RoHS:是 类别:编程器，开发系统 >> 评估板 - DC/DC 与 AC/DC（离线）SMPS 系列:- 产品培训模块:Obsolescence Mitigation Program 标准包装:1 系列:True Shutdown™ 主要目的:DC/DC，步升 输出及类型:1，非隔离 功率 - 输出:- 输出电压:- 电流 - 输出:1A 输入电压:2.5 V ~ 5.5 V 稳压器拓扑结构:升压 频率 - 开关:3MHz 板类型:完全填充 已供物品:板 已用 IC / 零件:MAX8969 |
| ISL6740EVAL3Z | 制造商:Intersil Corporation 功能描述:ISL6740 EVALUATION BOARD 3 - ROHS COMPLIANT - SOIC - DSL - Bulk 制造商:Intersil Corporation 功能描述:Power Management IC Development Tools ISL6740 EVAL RD 3 ROHS CMPL DSL |
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