参数资料
| 型号： | ISL6752AAZA-T |
| 厂商： | Intersil |
| 文件页数： | 10/16页 |
| 文件大小： | 0K |
| 描述： | IC REG CTRLR PWM CM 16-QSOP |
| 标准包装： | 2,500 |
| PWM 型： | 电流模式 |
| 输出数： | 6 |
| 频率 - 最大： | 2MHz |
| 占空比： | 100% |
| 电源电压： | 9 V ~ 16 V |
| 降压： | 无 |
| 升压： | 无 |
| 回扫： | 无 |
| 反相： | 无 |
| 倍增器： | 无 |
| 除法器： | 无 |
| Cuk： | 无 |
| 隔离： | 无 |
| 工作温度： | -40°C ~ 105°C |
| 封装/外壳： | 16-SSOP（0.154"，3.90mm 宽） |
| 包装： | 带卷 (TR) |
ISL6752
The values of R and C should be selected to control the rate
of rise of VERR to the desired soft-start duration. The
soft-start duration may be calculated from Equation 6.
where S n is the slope of the sawtooth signal and t SW is the
duration of the half-cycle. When an external ramp is added,
the modulator gain becomes Equation 8:
V SS – V be
t = – RC ? ln ? 1 – ------------------------------------------- ?
β
Fm = ------------------------------------ = --------------------------
? ?
? 0.001R ?
? VREF + ------------------- ?
S
(EQ. 6)
1 1
( S n + S e ) t SW m c S n t SW
where S e is slope of the external ramp and:
(EQ. 8)
m c = 1 + -------
where V SS is the soft-start clamp voltage, V be is the base
emitter voltage drop of the transistor, and β is the DC gain of
S e
S n
(EQ. 9)
the transistor. If β is sufficiently large, that term may be
ignored. The Schottky diode discharges the soft-start
capacitor so that the circuit may be reset quickly.
Gate Drive
The ISL6752 outputs are capable of sourcing and sinking
10mA (at rated VOH, VOL) and are intended to be used in
conjunction with integrated FET drivers or discrete bipolar
The criteria for determining the correct amount of external
ramp can be determined by appropriately setting the
damping factor of the double-pole located at half the
oscillator frequency. The double-pole will be critically
damped if the Q-factor is set to 1, and over-damped for
Q > 1, and under-damped for Q < 1. An under-damped
condition can result in current loop instability.
Q = -------------------------------------------------
totem pole drivers. The typical ON-resistance of the outputs
is 50 Ω .
1
π ( m c ( 1 – D ) – 0.5 )
(EQ. 10)
Overcurrent Operation
The cycle-by-cycle peak current control results in
where D is the percent of on-time during a half cycle. Setting
Q = 1 and solving for S e yields Equation 11:
S e = S n ? ? --- + 0.5 ? ------------- – 1 ?
pulse-by-pulse duty cycle reduction when the current
feedback signal exceeds 1.0V. When the peak current
exceeds the threshold, the active output pulse is
1 1
? ? π ? 1 – D ?
(EQ. 11)
V e = V n ? ? --- + 0.5 ? ------------- – 1 ?
? ? π
? 1 – D
?
immediately terminated. This results in a well controlled
decrease in output voltage as the load current increases
beyond the current limit threshold. The ISL6752 will operate
continuously in an overcurrent condition.
The propagation delay from CS exceeding the current limit
threshold to the termination of the output pulse is increased
by the leading edge blanking (LEB) interval. The effective
delay is the sum of the two delays and is nominally 105ns.
Slope Compensation
Peak current-mode control requires slope compensation to
improve noise immunity, particularly at lighter loads, and to
Since S n and S e are the on-time slopes of the current ramp
and the external ramp, respectively, they can be multiplied
by t ON to obtain the voltage change that occurs during t ON .
1 1
(EQ. 12)
where V n is the change in the current feedback signal during
the on-time and V e is the voltage that must be added by the
external ramp.
V n can be solved for in terms of input voltage, current
transducer components, and output inductance yielding
Equation 13:
V e = ---------------------------------------- ? -------- ? --- + D – 0.5 ?
N P ? π
N CT ? L O
prevent current loop instability, particularly for duty cycles
greater than 50%. Slope compensation may be
accomplished by summing an external ramp with the current
t SW ? V O ? R CS N S 1
?
V
(EQ. 13)
feedback signal or by subtracting the external ramp from the
voltage feedback error signal. Adding the external ramp to
the current feedback signal is the more popular method.
From the small signal current-mode model [1] it can be
shown that the naturally-sampled modulator gain, Fm,
without slope compensation, is expressed in Equation 7:
where R CS is the current sense burden resistor, N CT is the
current transformer turns ratio, L O is the output inductance,
V O is the output voltage, and N S and N P are the secondary
and primary turns, respectively.
The inductor current, when reflected through the isolation
transformer and the current sense transformer to obtain the
Fm = ------------------
1
S n t SW
(EQ. 7)
current feedback signal at the sense resistor yields
Equation 14:
N S ? R CS ? D ? t SW ? N S ? ?
N P ? N CT ?
V CS = ------------------------ ? I O + ------------------- ? V IN ? -------- – V O ? ?
2L O ? N P ? ?
V
(EQ. 14)
where V CS is the voltage across the current sense resistor
and I O is the output current at current limit.
10
FN9181.3
October 31, 2008
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| ISL6753AAZA | 功能描述:IC REG CTRLR PWM CM/VM 16-QSOP RoHS:是 类别:集成电路 (IC) >> PMIC - 稳压器 - DC DC 切换控制器 系列:- 产品培训模块:Lead (SnPb) Finish for COTS Obsolescence Mitigation Program 标准包装:2,500 系列:- PWM 型:电流模式 输出数:1 频率 - 最大:275kHz 占空比:50% 电源电压:18 V ~ 110 V 降压:无 升压:无 回扫:无 反相:无 倍增器:无 除法器:无 Cuk:无 隔离:是 工作温度:-40°C ~ 85°C 封装/外壳:8-SOIC（0.154"，3.90mm 宽） 包装:带卷 (TR) |
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