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参数资料
| 型号： | ISL8016IRAJZ-T |
| 厂商： | Intersil |
| 文件页数： | 3/22页 |
| 文件大小： | 0K |
| 描述： | IC REG BUCK SYNC ADJ 6A 20QFN |
| 产品培训模块： | Solutions for Industrial Control Applications |
| 标准包装： | 6,000 |
| 类型： | 降压（降压） |
| 输出类型： | 可调式 |
| 输出数： | 1 |
| 输出电压： | 0.6 V ~ 5.5 V |
| 输入电压： | 2.7 V ~ 5.5 V |
| PWM 型： | 电流模式 |
| 频率 - 开关： | 525kHz ~ 3.9MHz |
| 电流 - 输出： | 6A |
| 同步整流器： | 是 |
| 工作温度： | -40°C ~ 85°C |
| 安装类型： | 表面贴装 |
| 封装/外壳： | 20-VFQFN 裸露焊盘 |
| 包装： | 带卷 (TR) |
| 供应商设备封装： | 20-QFN（3x4） |
ISL8016
Pin Descriptions
PIN
1, 19, 20
2, 3, 4
5, 6, 7
8
9
10
11
12
13
14
15
16, 17
18
SYMBOL
PGND
PHASE
VIN
PG
SYNCOUT
SYNCIN
EN
FS
VSET
ISET
SS
COMP, VFB
SGND
EPAD
3
DESCRIPTION
Power ground.
Switching node connection. Connect to one terminal of the inductor.
Input supply voltage. Connect two 22μF ceramic capacitors to power ground.
Power-good is an open-drain output. Use 10k Ω to 100k Ω pull-up resistor connected between VIN and
PG. At power-up or EN HI, PG rising edge is delayed by 1ms from the output reaching regulation.
This pin outputs a 250μA current source that is turned on at the rising edge of the internal clock or
SYNCIN. When SYNCOUT voltage reaches 1V, a reset circuit will activate and discharge SYNCOUT to 0V.
SYNCOUT is held at 0V in PFM light load to reduce quiescent current.
Mode Selection pin. Connect to logic high or input voltage VIN for PWM mode. Connect to logic low or
ground for PFM mode. Connect to an external function generator for synchronization with the positive
edge trigger. There is an internal 1M Ω pull-down resistor to prevent an undefined logic state if SYNCIN
is floating.
Regulator enable pin. Enables the output when driven to high. Shuts down the chip and discharges the
output capacitor when driven to low. There is an internal 1M Ω pull-down resistor to prevent an
undefined logic state in case of EN pin float.
This pin sets the oscillator switching frequency, using a resistor, R FS , from the FS pin to GND. The
frequency of operation may be programmed between 500kHz to 4MHz. The default frequency is 1MHz
and configured for internal compensation if FS is connected to VIN.
VSET is the output margining setting of the regulators. Connect to SGND for -10%, keep it floating for
no margining, and connect to VIN for +10%.
ISET is the peak output current limit and SKIP current limit setting of the regulators. Connect to SGND
for 2A, to VIN for 4A, and keep it floating for 6A.
SS is used to adjust the soft-start time. Set to SGND for internal 1ms rise time. Connect a capacitor
from SS to SGND to adjust the soft-start time. Do not use more than 33nF per IC.
The feedback network of the regulator, VFB, is the negative input to the transconductance error
amplifier. COMP is the output of the amplifier if the FS resistor is used. If internal compensation is used
(FS = VIN), the comp pin should be tied to SGND. The output voltage is set by an external resistor divider
connected to VFB. With a properly selected divider, the output voltage can be set to any voltage
between VIN and the 0.6V reference. While internal compensation offers a solution for many typical
applications, an external compensation network may offer improved performance for some designs.
In addition to regulation, VFB is also used to determine the state of PG.
Short VFB to OUTPUT when using one of the available fixed VOUT options.
Signal ground.
The exposed pad must be connected to the SGND pin for proper electrical performance. Place as many
vias as possible under the pad connecting to the system GND plane for optimal thermal performance.
FN7616.1
May 5, 2011
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