参数资料
| 型号： | ISL8101IRZ-T |
| 厂商： | Intersil |
| 文件页数： | 12/20页 |
| 文件大小： | 0K |
| 描述： | IC PWM CTRLR BUCK 2PHASE 24-QFN |
| 标准包装： | 6,000 |
| 应用： | 控制器，Intel VRM9，VRM10，AMD Hammer 应用 |
| 输入电压： | 4.6 V ~ 12 V |
| 输出数： | 1 |
| 输出电压： | 0.6 V ~ 2.3 V |
| 工作温度： | -40°C ~ 85°C |
| 安装类型： | 表面贴装 |
| 封装/外壳： | 24-VFQFN 裸露焊盘 |
| 供应商设备封装： | 24-QFN（4x4） |
| 包装： | 带卷 (TR) |
ISL8101
OVERVOLTAGE PROTECTION
The ISL8101 benefits from a multi-tiered approach to
overvoltage protection.
A pre-POR mechanism is at work while the chip does not
have sufficient bias voltage to initiate an active response to
chosen to enable the ISL8101 as the 12V input exceeds
approximately 9.75V. Additionally, an open-drain or open-
collector device can be used to wire-AND a second (or
multiple) control signal, as shown in Figure 6. To defeat the
threshold-sensitive enable, connect ENLL to VCC directly or
via a pull-up resistor.
an OV situation. Thus, while VCC is below its POR level, the
lower drives are three-stated and internal 5k Ω (typically)
resistors are connected from PHASE to their respective
LGATE pins. As a result, output voltage, duplicated at the
PHASE nodes via the output inductors, is effectively
ISL8101
EXTERNAL CIRCUIT
+5V
+12V
clamped at the lower MOSFETs’ threshold level. This
approach ensures no catastrophic output voltage can be
ENABLE
COMPARATOR
V CC
15k Ω
developed at the output of an ISL8101-based regulator (for
most typical applications).
The pre-POR mechanism is removed once the bias is above
POR
CIRCUIT
+
-
ENLL
1k Ω
OFF
the POR level, and a fixed-threshold OVP goes into effect.
Based on the specific chip configuration, the OVP goes into
effect once the voltage sensed at the FB pin exceeds about
0.61V
ON
1.65V (Hammer/VR10) or 1.95V (VR9 configuration). Should
the output voltage exceed these thresholds, the lower
MOSFETs are turned on.
During soft-start, the OVP threshold changes to the higher of
the fixed threshold (1.65V/1.95V) or the DAC setting plus
200mV. At the end of the soft-start, the OVP threshold
changes to the DAC setting plus 200mV.
In any of the described post-POR functionality, OVP results
in the turn-on of the lower MOSFETs. Once turned on, the
lower MOSFETs are only turned off when the output voltage
drops below the OV comparator ’s hysteretic threshold. The
OVP process repeats if the voltage rises back above the
designated threshold. The occurrence of an OVP event does
not latch the controller; should the phenomenon be
transitory, the controller resumes normal operation following
such an event.
ON/OFF CONTROL
The internal power-on reset circuit (POR) prevents the
ISL8101 from starting before the bias voltage at VCC and
PVCC reach the rising POR thresholds, as defined in
“Electrical Specifications” on page 4. The POR levels are
sufficiently high to guarantee that all parts of the ISL8101
can perform their functions properly once bias is applied to
FIGURE 6. START-UP COORDINATION USING THRESHOLD-
SENSITIVE ENABLE (ENLL) PIN
The ‘11111’ VID code is reserved as a signal to the controller
that no load is present. The controller is disabled while
receiving this VID code and will subsequently start up upon
receiving any other code.
In summary, for the ISL8101 to operate, the following
conditions need be met: V CC and P VCC must be greater
than their respective POR thresholds, the voltage at ENLL
must be greater than 0.61V, and VID has to be different than
‘11111’. Once all these conditions are met, the controller
immediately initiates a soft-start sequence.
SOFT-START
The soft-start function allows the converter to bring up the
output voltage in a controlled fashion, resulting in a linear
ramp-up. Following a delay of 16 PHASE clock cycles (about
70μs) between enabling the chip and the start of the ramp,
the output voltage progresses at a fixed rate of 12.5mV per
16 PHASE clock cycles.
Thus, the soft-start period (not including the 70μs wait) up to
a given voltage, V DAC , can be approximated by Equation 7.
t SS = ---------------------------------
the part. While bias is below the rising POR thresholds, the
controlled MOSFETs are kept in an off state.
V DAC ? 1280
f S
(EQ. 7)
A secondary disablement feature is available via the
threshold-sensitive enable input (ENLL). This optional
feature prevents the ISL8101 from operating until a certain
other voltage rail is available and above some selectable
threshold. For example, when down-converting off a 12V
input, it may be desirable the ISL8101-based converter does
not start up until the power input is sufficiently high. The
schematic in Figure 6 demonstrates coordination of the
ISL8101 with such a rail; the resistor components are
12
where V DAC is the DAC-set VID voltage, and f S is the
switching frequency (typically 222kHz).
The ISL8101 also has the ability to start-up into a
pre-charged output, without causing any unnecessary
disturbance. The FB pin is monitored during soft-start, and
should it be higher than the equivalent internal ramping
reference voltage, the output drives hold both MOSFETs off.
Once the internal ramping reference exceeds the FB pin
FN9223.1
July 28, 2008
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相关代理商/技术参数 |
参数描述 |
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| ISL8102 | 制造商:INTERSIL 制造商全称:Intersil Corporation 功能描述:Two-Phase Buck PWM Controller with High Current Integrated MOSFET Drivers |
| ISL8102CRZ | 功能描述:IC REG CTRLR BUCK PWM VM 32-QFN RoHS:是 类别:集成电路 (IC) >> PMIC - 稳压器 - DC DC 切换控制器 系列:- 标准包装:2,500 系列:- PWM 型:电流模式 输出数:1 频率 - 最大:500kHz 占空比:100% 电源电压:8.2 V ~ 30 V 降压:无 升压:无 回扫:是 反相:无 倍增器:无 除法器:无 Cuk:无 隔离:是 工作温度:0°C ~ 70°C 封装/外壳:8-DIP（0.300"，7.62mm） 包装:管件 产品目录页面:1316 (CN2011-ZH PDF) |
| ISL8102CRZ-T | 功能描述:IC REG CTRLR BUCK PWM VM 32-QFN RoHS:是 类别:集成电路 (IC) >> PMIC - 稳压器 - DC DC 切换控制器 系列:- 标准包装:4,000 系列:- PWM 型:电压模式 输出数:1 频率 - 最大:1.5MHz 占空比:66.7% 电源电压:4.75 V ~ 5.25 V 降压:是 升压:无 回扫:无 反相:无 倍增器:无 除法器:无 Cuk:无 隔离:无 工作温度:-40°C ~ 85°C 封装/外壳:40-VFQFN 裸露焊盘 包装:带卷 (TR) |
| ISL8102EVAL1 | 功能描述:EVAL BOARD 1 FOR ISL8102 RoHS:否 类别:编程器，开发系统 >> 评估板 - DC/DC 与 AC/DC（离线）SMPS 系列:* 标准包装:1 系列:- 主要目的:DC/DC，步降 输出及类型:1，非隔离 功率 - 输出:- 输出电压:3.3V 电流 - 输出:3A 输入电压:4.5 V ~ 28 V 稳压器拓扑结构:降压 频率 - 开关:250kHz 板类型:完全填充 已供物品:板 已用 IC / 零件:L7981 其它名称:497-12113STEVAL-ISA094V1-ND |
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