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参数资料
| 型号： | ISL8107EVAL2Z |
| 厂商： | Intersil |
| 文件页数： | 15/16页 |
| 文件大小： | 0K |
| 描述： | EVAL BOARD 2 FOR ISL8107 |
| 标准包装： | 1 |
| 系列： | * |
ISL8107
.
Locate the ISL8107 within 2 to 3 inches of the MOSFET, Q1,
(1 inch or less for 500kHz or higher operation). The circuit
VCC
PVCC
ISL8107
VCC
C BP_VCC
C BP_PVCC
VIN
traces for the MOSFETs’ gate and source connections from
the ISL8107 must be sized to handle up to 2A peak current.
Minimize any leakage current paths on the ENSS pin and
locate the capacitor, C ENSS close to the ENSS pin as the
internal current source is only 33μA. Provide local V CC
decoupling between VCC and GND pins. Locate the
capacitor, C BOOT as close as practical to the BOOT pin and
UGATE
Q 1
C IN
the phase node.
BOOT
GND
PHASE
ENSS
PGND
C IN
C ENSS
L OUT
C OUT
V OUT
KEY
TRACE SIZED FOR 2A PEAK CURRENT
SHORT TRACE, MINIMUM IMPEDANCE
ISLAND ON POWER PLANE LAYER
ISLAND ON CIRCUIT AND/OR POWER PLANE LAYER
VIA CONNECTION TO GROUND PLANE
FIGURE 17. PRINTED CIRCUIT BOARD POWER PLANES
AND ISLANDS
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Intersil Corporation’s quality certifications can be viewed at www.intersil.com/design/quality
Intersil products are sold by description only. Intersil Corporation reserves the right to make changes in circuit design, software and/or specifications at any time without
notice. Accordingly, the reader is cautioned to verify that data sheets are current before placing orders. Information furnished by Intersil is believed to be accurate and
reliable. However, no responsibility is assumed by Intersil or its subsidiaries for its use; nor for any infringements of patents or other rights of third parties which may result
from its use. No license is granted by implication or otherwise under any patent or patent rights of Intersil or its subsidiaries.
For information regarding Intersil Corporation and its products, see www.intersil.com
15
FN6605.0
October 29, 2008
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