参数资料
| 型号： | ISL8107IRZ |
| 厂商： | Intersil |
| 文件页数： | 7/16页 |
| 文件大小： | 0K |
| 描述： | IC REG CTRLR BUCK PWM VM 16-QFN |
| 标准包装： | 60 |
| PWM 型： | 电压模式 |
| 输出数： | 1 |
| 频率 - 最大： | 600kHz |
| 电源电压： | 9 V ~ 75 V |
| 降压： | 是 |
| 升压： | 无 |
| 回扫： | 无 |
| 反相： | 无 |
| 倍增器： | 无 |
| 除法器： | 无 |
| Cuk： | 无 |
| 隔离： | 无 |
| 工作温度： | -40°C ~ 85°C |
| 封装/外壳： | 16-VQFN 裸露焊盘 |
| 包装： | 管件 |
ISL8107
Functional Pin Description
VFF (Pin 1)
The voltage at this pin is used for input voltage feed forward
compensation and sets the internal oscillator ramp peak to
peak amplitude at 0.11*VFF. The oscillator ramp amplitude
varies from approximately 1V to 8.5V as VFF changes from
9V to 75V to maintain constant frequency and provide feed
forward compensation.
An external RC filter may be required at this pin in noisy
input environments.
OCSET (Pin 2)
The current limit is set by placing a resistor, R OCSET and
capacitor, C OCSET , between this pin and the drain of the
MOSFET. The maximum allowable R OCSET resistor is
50k Ω . A 104μA current source develops a voltage across
R OCSET which is then compared with the voltage developed
across the MOSFET when on. An initial ~200ns blanking
period is used to eliminate the sampling error due to
switching noise before the current is measured.
VCC (Pin 3)
VCC is power connection for the ISL8107. The pin should be
connected to a 9V to 75V bias supply and must be well
decoupled to signal ground (SGND) with a ceramic
capacitor.
The voltage at this pin must always be equal to or less than
the voltage at VFF pin.
SYNC (Pin 4)
The switching frequency can be synchronized to an external
clock through this pin. When the sync function is not used,
this pin must be tied to ground. If the sync function is used,
the R T /C T natural frequency must be set to a frequency
lower than the sync input frequency. The termination of the
ramp is synchronized with the rising edge of the sync input
signal.
RT/CT (Pin 5)
A resistor to VFF and a capacitor to GND determines the
frequency of the sawtooth oscillator. The resistor should be
in the range of 20k to 100k, the capacitor range should be in
the range of 470pF to 1.2nF.
When the controller is disabled, the voltage at RT/CT pin
rises up to VFF. Hence, the voltage rating of the CT
capacitor must be sufficient to support the maximum VFF.
SGND (Pin 6)
Signal ground for the IC. All voltage levels are measured
with respect to this pin.
FB (Pin 7)
This is the feedback pin. The feedback ratio is set by an
external resistor divider connected to the output.
7
COMP (Pin 8)
This pin is connected to the output of the transconductance
error amplifier and is used to compensate the feedback loop.
VBG (Pin 9)
Band gap reference output. A 0.01μF capacitor to SGND is
required for decoupling this signal. This pin should not be
loaded.
PGOOD (Pin 10)
This pin provides a power good status. It is an open drain
output that is asserted when the voltage at FB pin is within
±14% of the reference voltage.
PGND (Pin 11)
T his pin provides the power ground to the IC. Tie this pin to
the ground plane through the lowest impedance connection.
EN/SS (Pin 12)
This pin provides enable/disable function and soft-start
timing function for the PWM output. The IC is disabled when
this pin is held below 0.5V.
PHASE (Pin 13)
Connect this pin to the source of MOSFET. This pin provides
the return path for the gate drive current. During normal
switching, this pin is also used for current limiting
measurements.
UGATE (Pin 14)
This pin provides the drive for the MOSFET and should be
connected to its gate.
BOOT (Pin 15)
This pin provides the bootstrap bias for the gate driver. A
2.2 Ω resistor may be placed in series with the bootstrap
diode to prevent over charging of the BOOT capacitor during
normal operation.
PVCC (Pin 16)
This pin is the output of the internal series linear regulator. A
minimum 1μF capacitor is required for decoupling PVCC to
PGND. For proper operation the PVCC capacitor must be
within 150 mils of the PVCC and the PGND pins and must
be connected to these pins with dedicated traces.
Exposed Thermal Pad
This pad is electrically isolated. Connect this pad to the
signal ground plane using at least five vias for a robust
thermal conduction path.
FN6605.0
October 29, 2008
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