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参数资料
| 型号： | ISL8118EVAL1Z |
| 厂商： | Intersil |
| 文件页数： | 8/20页 |
| 文件大小： | 0K |
| 描述： | EVALUATION BOARD FOR ISL8118 |
| 标准包装： | 1 |
| 主要目的： | DC/DC，步降 |
| 输出及类型： | 1，非隔离 |
| 输出电压： | 1.8V |
| 电流 - 输出： | 25A |
| 输入电压： | 4.5 ~ 20 V |
| 稳压器拓扑结构： | 降压 |
| 频率 - 开关： | 300kHz |
| 板类型： | 完全填充 |
| 已供物品： | 板 |
| 已用 IC / 零件： | ISL8118 |
ISL8118
Electrical Specifications
Recommended Operating Conditions, Unless Otherwise Noted. Parameters with MIN and/or MAX limits are
100% tested at +25°C, unless otherwise specified. Temperature limits established by characterization and are
not production tested. (Continued)
PARAMETER
TGATE Source Saturation Current
TGATE Sink Resistance
TGATE Sink Saturation Current
Bgate Source Resistance
Bgate Source Saturation Current
Bgate Sink Resistance
Bgate Sink Saturation Current
SYMBOL
I TGATE
R TGATE
I TGATE
R BGATE
I BGATE
R BGATE
I BGATE
TEST CONDITIONS
V TGATE-LX = 2.5V, PVCC = 5.0V
500mA Sink Current, PVCC = 5.0V
V TGATE-LX = 2.5V, PVCC = 5.0V
500mA Source Current, PVCC = 5.0V
V BGATE = 2.5V, PVCC = 5.0V
500mA Sink Current, PVCC = 5.0V
V BGATE = 2.5V, PVCC = 5.0V
MIN
-
-
-
-
-
-
-
TYP
2.0
1.0
2.0
1.0
2.0
0.4
4.0
MAX
-
-
-
-
-
-
-
UNITS
A
Ω
A
Ω
A
Ω
A
INTERNAL LINEAR REGULATOR
Maximum Current
I VIN
-
200
-
mA
Saturated Equivalent Impedance
Linear Regulator Voltage
Maximum VIN DV/DT
R LIN
PVCC
VIN DV/DT_Max
VIN = 3.3V
VIN = 20V, Load = 0 to 100mA
V IN = 0V to V IN step, PVCC < 2.0V at V IN
-
5.3
-
2
5.5
1
3.9
5.71
-
Ω
V
V/μs
application; V IN > 6.5V
V IN = 2.0V to V IN step, 2.0V < PVCC at V IN
-
0.05
-
V/μs
application; V IN > 6.5V
EXTERNAL LINEAR REGULATOR
Maximum Sinking Drive Current
LIN_DRV
LIN_DRV = VIN = 20V
LIN_DRV = VIN = 3.3V
1.30
1.67
4.17
3.88
5.30
4.67
mA
mA
OVERCURRENT PROTECTION (OCP)
Bottom Side OCP (BSOC)
Current Source
BSOC Maximum Offset Error
Top Side OCP (TSOC) Current
I BSOC
I BSOC_OFSET
I TSOC
BSOC = 0V to VCC - 1.0V, T A = 0°C to +70°C
BSOC = 0V to VCC - 1.0V, T A = -40°C to +85°C
Vcc = 2.9V and 5.6V t SAMPLE < 10μs
TSOC = 0.8V to 22V T A = 0°C to +70°C
86
84
-
91
100
100
±2
100
107
109
-
106
μA
μA
mV
μA
Source
I TSOC_LOW
TSOC = 0.8V to 22V T A = -40°C to +85°C
TSOC = 0.3V to 0.8V
89
84
100
-
107
107
μA
μA
TSOC Maximum Offset Error
I TSOC_OFSET
VCC = 2.9V and 5.5V t SAMPLE < 10μs
-
±2
-
mV
POWER GOOD MONITOR
Undervoltage Rising Trip Point
Undervoltage Falling Trip Point
Overvoltage Rising Trip Point
Overvoltage Falling Trip Point
V UVR
V UVF
V OVR
V OVF
-7%
-13%
13%
7%
-9%
-15%
15%
9%
-11%
-17%
17%
11%
V SS
V SS
V SS
V SS
PGOOD Delay
PGOOD Delay Source Current
PGOOD Delay Threshold Voltage
PGOOD Low Output Voltage
Maximum Sinking Current
Maximum Open Drain Voltage
t PGDLY
I PGDLY
V PGDLY
I PG_LOW
I PG_MAX
V PG_MAX
C PGDLY = 0.1μF
I PGOOD = 5mA
V PGOOD = 0.8V
VCC = 3.3V
-
17
1.45
-
23
-
7.1
21
1.49
-
-
6
-
24
1.52
0.150
-
-
ms
μA
V
V
mA
V
MARGINING CONTROL
Minimum Margining Voltage of
V MARG
R MARG = 10k Ω , R OFSN = 6.01k Ω ,
-187
-197
-209
mV
Internal Reference
MAR_CRTL = 0V
Maximum Margining Voltage of
V MARG
R MARG = 10k Ω , R OFSP = 6.01k Ω ,
185
197
208
mV
Internal Reference
8
MAR_CRTL = VCC
FN6325.2
November 29, 2012
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