参数资料
型号: ISL8200MEVAL2PHZ
厂商: Intersil
文件页数: 15/23页
文件大小: 0K
描述: EVAL BOARD FOR ISL8200M
产品培训模块: Solutions for Industrial Control Applications
标准包装: 1
系列: *
ISL8200M
when recovering from faults. A 1nF capacitor is
recommended as a starting value for typical application.
The voltage on the FF pin needs to be above 0.7V prior to
soft-start and during PWM switching to ensure reliable
regulation. In a typical application, FF pin can be shorted
to EN pin.
Fault Handshake
allowable pre-charged level is 113%. If the pre-charged
level is above 113% but below 120%, the output will
hiccup between 113% (LGATE turns on) and 87%
(LGATE turns off) while EN is pulled low. If the pre-
charged load voltage is above 120% of the targeted
output voltage, then the controller will be latched off and
not be able to power-up.
t SS = -------------
In a multi-module system, with the EN pins wired OR’ed
together, all modules can immediately turn off, at one
time, when a fault condition occurs in one or more
modules. A fault would pull the EN pin low, disabling all
the modules and would not creating current bounce.
Thus, no single channel would be over stressed when a
fault occurs.
FIRST PWM PULSE
0.0V
-100mV
SS Settling at VREF + 100mV
VOUT TARGET VOLTAGE
2560
f SW
t SS_DLY ≈ ------------
Since the EN pins are pulled down under fault conditions,
the pull-up resistor (RUP) should be scaled to sink no
more than 5mA current from EN pin. Essentially, the EN
pins cannot be directly connected to VCC.
384
F SW
FIGURE 22. SOFT-START WITH VOUT = 0V
Soft-Start
The ISL8200M has an internal digital pre-charged
soft-start circuitry, which has a rise time inversely
proportional to the switching frequency and is
determined by an digital counter that increments with
FIRST PWM PULSE
INIT. VOUT
SS Settling at VREF + 100mV
VOUT TARGET VOLTAGE
every pulse of the phase clock. The full soft-start time
from 0V to 0.6V can be estimated by Equation 5.
-100mV
FIGURE 23. SOFT-START WITH VOUT < TARGET
t SS = -------------
2560
f SW
(EQ. 5)
VOLTAGE
The ISL8200M has the ability to work under a pre-
charged output. The PWM outputs will not feed to the
drivers until the first PWM pulse is seen. The low side
MOSFET is being held low for first clock cycle to provide
charge for the bootstrap capacitor. If the pre-charged
output voltage is greater than the final target level but
less than the 113% setpoint, switching will not start until
the output voltage is reduced to the target voltage and
the first PWM pulse is generated. The maximum
OV = 113%
FIRST PWM PULSE
VOUT TARGET VOLTAGE
FIGURE 24. SOFT-START WITH VOUT BELOW OV BUT
ABOVE FINAL TARGET VOLTAGE
I EN_HYS
R ? V
EN_REF
V EN_FTH – V EN_REF
V EN_HYS
R UP = -----------------------------
UP
R DOWN = ---------------------------------------------------------------
V EN_FTH = V EN_RTH – V EN_HYS
V CC_FF
G RAMP = 1.25
VCC - 1.4V
UPPER LIMIT
Δ V
RAMP
= LIMIT(V
CC_FF
× G
RAMP
, VCC - 1.4V - V
RAMP_OFFSET
)
0.8V
LIMITER
SAWTOOTH
AMPLITUDE
( Δ V RAMP )
VIN
FF
V RAMP_OFFSET = 1.0V
LOWER LIMIT
(RAMP OFFSET)
0.8V
SYSTEM DELAY
R UP
R DOWN
EN
I EN_HYS = 30μA
384 Clock
Cycles
SOFT-START
OV, OT, OC, AND PLL LOCKING FAULTS
FIGURE 25. SIMPLIFIED ENABLE AND VOLTAGE FEEDFORWARD CIRCUIT
15
FN6727.1
February 26, 2010
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