参数资料
| 型号： | ISL85001IRZ-T |
| 厂商： | Intersil |
| 文件页数： | 14/17页 |
| 文件大小： | 0K |
| 描述： | IC REG BUCK ADJ 1A 12DFN |
| 标准包装： | 6,000 |
| 类型： | 降压（降压） |
| 输出类型： | 可调式 |
| 输出数： | 1 |
| 输出电压： | 0.6 V ~ 19 V |
| 输入电压： | 4.5 V ~ 25 V |
| PWM 型： | 电压模式 |
| 频率 - 开关： | 500kHz |
| 电流 - 输出： | 1A |
| 同步整流器： | 无 |
| 工作温度： | -40°C ~ 85°C |
| 安装类型： | 表面贴装 |
| 封装/外壳： | 12-VFDFN 裸露焊盘 |
| 包装： | 带卷 (TR) |
| 供应商设备封装： | 12-DFN（4x3） |
ISL85001
OSC
DRIVER
V IN
Compensation Break Frequency Equations
F Z1 = ------------------------------------
F P1 = ---------------------------------------------------------
2 π x R 2 x ? ---------------------- ?
DV OSC
PWM
COMPARATOR
-
+
D
L O
PHASE
C O
V DDQ
1
2 π x R 2 x C 2
1
? C 1 x C 2 ?
? C 1 + C 2 ? (EQ. 8)
F Z2 = -------------------------------------------------------
F P2 = ------------------------------------
Z FB
V E/A
ESR
(PARASITIC)
1
2 π x ( R 1 + R 3 ) x C 3
1
2 π x R 3 x C 3
-
+
ERROR
AMP
Z IN
REFERENCE
Figure 22 shows an asymptotic plot of the DC/DC converter’s
gain vs frequency. The actual Modulator Gain has a high gain
peak due to the high Q factor of the output filter and is not shown
DETAILED COMPENSATION COMPONENTS
in Figure 22. Using the previously mentioned guidelines should
C 2
C 1
R 2
Z FB
C 3
Z IN
R 3
V OUT
give a Compensation Gain similar to the curve plotted. The open
loop error amplifier gain bounds the compensation gain. Check
the compensation gain at F P2 with the capabilities of the error
amplifier. The Closed Loop Gain is constructed on the graph of
COMP
R 1
Figure 4 by adding the Modulator Gain (in dB) to the
Compensation Gain (in dB). This is equivalent to multiplying the
-
+
FB
R 4
modulator transfer function to the compensation transfer
function and plotting the gain.
ISL85001
REFERENCE
FIGURE 21. VOLTAGE-MODE BUCK CONVERTER COMPENSATION
DESIGN AND OUTPUT VOLTAGE SELECTION
100
80
60
F Z1 F Z2
F P1
F P2
OPEN LOOP
ERROR AMP GAIN
Modulator Break Frequency Equations
40
20
20LOG
(R 2 /R 1 )
20LOG
F LC = -------------------------------------------
F ESR = --------------------------------------------
1
2 π x LO x CO
1
2 π x ESR x C O
(EQ. 7)
0
-20
MODULATOR
GAIN
(V IN / Δ V OSC )
COMPENSATION
GAIN
F ESR
The compensation network consists of the error amplifier
(internal to the ISL85001) and the impedance networks Z IN and
Z FB . The goal of the compensation network is to provide a closed
loop transfer function with the highest 0dB crossing frequency
-40
-60
10
100
1k
F LC
10k 100k
FREQUENCY (Hz)
1M
CLOSED LOOP
GAIN
10M
(f 0dB ) and adequate phase margin. Phase margin is the
difference between the closed loop phase at f 0dB and 180°.
Equation 8 relates the compensation network’s poles, zeros and
gain to the components (R 1 , R 2 , R 3 , C 1 , C 2 , and C 3 ) in
Figure 22. Use the following guidelines for locating the poles and
zeros of the compensation network:
1. Pick Gain (R 2 /R 1 ) for desired converter bandwidth.
2. Place 1 ST Zero Below Filter’s Double Pole (~75% F LC ).
3. Place 2 ND Zero at Filter’s Double Pole.
4. Place 1 ST Pole at the ESR Zero.
5. Place 2 ND Pole at Half the Switching Frequency.
6. Check Gain against Error Amplifier’s Open-Loop Gain.
7. Estimate Phase Margin - Repeat if Necessary.
14
FIGURE 22. ASYMPTOTIC BODE PLOT OF CONVERTER GAIN
The compensation gain uses external impedance networks Z FB
and Z IN to provide a stable, high bandwidth (BW) overall loop. A
stable control loop has a gain crossing with -20dB/decade slope
and a phase margin greater than 45°. Include worst case
component variations when determining phase margin.
A more detailed explanation of voltage mode control of a buck
regulator can be found in TB417 , entitled “Designing Stable
Compensation Networks for Single Phase Voltage Mode Buck
Regulators.”
Layout Considerations
Layout is very important in high frequency switching converter
design. With power devices switching efficiently between 100kHz
and 600kHz, the resulting current transitions from one device to
another cause voltage spikes across the interconnecting
impedances and parasitic circuit elements. These voltage spikes
can degrade efficiency, radiate noise into the circuit, and lead to
device overvoltage stress. Careful component layout and printed
circuit board design minimizes these voltage spikes.
FN6769.2
May 29, 2012
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