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参数资料
| 型号： | ISL85033EVAL2Z |
| 厂商： | Intersil |
| 文件页数： | 3/26页 |
| 文件大小： | 0K |
| 描述： | EVAL BOARD2 FOR ISL85033 |
| 标准包装： | 1 |
| 系列： | * |
ISL85033
Pin Descriptions (Continued)
PIN NUMBER
23
24
25
26
27
22, 28
-
SYMBOL
SYNCOUT
SYNCIN
SGND
NC
FS
PGOOD1, PGOOD2
PD
PIN DESCRIPTION
Synchronization output. Provides a signal that is the inverse of the SYNCIN signal.
Connect to an external signal for synchronization from 300kHz to 2MHz (negative edge trigger). SYNCIN is
not allowed to be floating.
When SYNCIN = logic 0, PHASE1 and PHASE2 are running at 180° out-of-phase.
When SYNCIN = logic 1, PHASE1 and PHASE2 are running at 0° in-phase.
When SYNCIN = an external clock, PHASE1 and PHASE2 are running at 180° out-of-phase.
External SYNC frequency applied to the SYNCIN pin should be at least 2.4 times the internal switching
frequency setting.
Signal ground connections. The exposed pad must be connected to SGND and soldered to the PCB. All
voltage levels are measured with respect to this pin.
This is a no connection pin.
Frequency selection pin. Tie to VCC for 500kHz switching frequency. Connect a resistor to GND for
adjustable frequency from 300kHz to 2MHz.
Open drain power-good output that is pulled to ground when the output voltage is below regulation limits
or during the soft-start interval. There is an internal 5M Ω internal pull-up resistor.
The exposed pad must be connected to the system GND plane with as many vias as possible for proper
electrical and thermal performance.
Typical Application Schematics
V OUT2
R 5
25.5k
C 4
68pF
R 6
8.06k
C 5
470pF
R 2
8.06k
C 2
470pF
R 1
42.2k
C 1
68pF
V OUT1
R 8
69.8k
R 4
69.8k
20
21
1
2
V OUT2
3A
C 13
47μF
L 2
7μH
D 2
B340B
VCC
VCC
VCC
FS 27
SS2 19
SS1 3
PGOOD2
22
PGOOD1
28
PHASE2
15/16
C 12
10nF
BOOT2 17
ISL85033
8/9 VIN1
VIN2
13/14
10μF
PHASE1
6/7
5 BOOT1
C 72
C 8
10nF
C 71
20μF
L1
7μH
D 1
B340B
C 9
47μF
V OUT1
3A
24
23
12
26
10 25
11
4.7μF
FIGURE 2. DUAL 3A OUTPUT (VIN RANGE FROM 4.5V TO 28V)
3
FN6676.6
February 23, 2012
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