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参数资料
| 型号： | ISL8510EVAL1Z |
| 厂商： | Intersil |
| 文件页数： | 18/21页 |
| 文件大小： | 0K |
| 描述： | EVALUATION BOARD FOR ISL8510 |
| 标准包装： | 1 |
| 主要目的： | DC/DC，LDO 步降 |
| 输出及类型： | 3，非隔离 |
| 输出电压： | 3.3V，1.2V，1.8V |
| 电流 - 输出： | 1A，500mA，500mA |
| 输入电压： | 4.5 ~ 25 V |
| 稳压器拓扑结构： | 降压 |
| 频率 - 开关： | 500kHz |
| 板类型： | 完全填充 |
| 已供物品： | 板 |
| 已用 IC / 零件： | ISL8510 |
ISL8510
to supply the current needed each time the switching
MOSFET turns on. Place the small ceramic capacitors
physically close to the MOSFET VIN pins (switching
MOSFET drain) and the Schottky diode anode.
The important parameters for the bulk input capacitance are
the voltage rating and the RMS current rating. For reliable
operation, select bulk capacitors with voltage and current
ratings above the maximum input voltage and largest RMS
current required by the circuit. Their voltage rating should be
at least 1.25x greater than the maximum input voltage, while
a voltage rating of 1.5x is a conservative guideline. For most
cases, the RMS current rating requirement for the input
capacitor of a buck regulator is approximately 1/2 the DC
180°. Equations 10 through 13 relate the compensation
network’s poles, zeros and gain to the components (R 1 , R 2 ,
R 3 , C 1 , C 2 , and C 3 ) in Figure 31. Use these guidelines for
locating the poles and zeros of the compensation network:
1. Pick Gain (R 2 /R 1 ) for desired converter bandwidth.
2. Place 1st Zero Below Filter’s Double Pole (~75% f LC ).
3. Place 2nd Zero at Filter ’s Double Pole.
4. Place 1st Pole at the ESR Zero.
5. Place 2nd Pole at Half the Switching Frequency.
6. Check Gain against Error Amplifier ’s Open-Loop Gain.
7. Estimate Phase Margin - Repeat if Necessary.
load current.
OSC
DRIVER
V IN
The maximum RMS current required by the regulator may be
PWM
COMPARATOR
L O
V DDQ
-------------- × ? I OUT
+ ------ × ? ----------------------------- × -------------- ? ?
I RMS
?
V IN ? ?
?
L × f s
V IN
-
C O
-
closely approximated through Equation 7:
V OUT 2 1 V IN – V OUT V OUT 2
=
MAX MAX 12
(EQ. 7)
For a through hole design, several electrolytic capacitors
may be needed. For surface mount designs, solid tantalum
capacitors can be used, but caution must be exercised with
regard to the capacitor surge current rating. These
Δ V OSC
+
Z FB
V E/A
+
ERROR
AMP
DRIVER
Z IN
REFERENCE
PHASE
ESR
(PARASITIC)
capacitors must be capable of handling the surge-current at
DETAILED COMPENSATION COMPONENTS
power-up. Some capacitor series available from reputable
manufacturers are surge current tested.
Feedback Compensation
Figure 30 highlights the voltage-mode control loop for a
synchronous-rectified buck converter. The output voltage
C 1
C 2
COMP
R 2
Z FB
C 3
Z IN
R 1
R 3
V DDQ
(V OUT ) is regulated to the Reference voltage level. The error
amplifier output (V E/A ) is compared with the oscillator (OSC)
triangular wave to provide a pulse-width modulated (PWM)
-
+
FB
R 4
V DDQ = 0.8 × ? 1 + ------ 1 - ?
wave with an amplitude of V IN at the PHASE node. The
PWM wave is smoothed by the output filter (L O and C O ).
The modulator transfer function is the small-signal transfer
function of V OUT /V E/A . This function is dominated by a DC
Gain and the output filter (L O and C O ), with a double pole
break frequency at f LC and a zero at f ESR . The DC Gain of
the modulator is simply the input voltage (V IN ) divided by the
peak-to-peak oscillator voltage Δ V OSC .
ISL8510
REFERENCE
? R ?
? R 4 ?
FIGURE 30. VOLTAGE-MODE BUCK CONVERTER
COMPENSATION DESIGN AND OUTPUT
VOLTAGE SELECTION
Compensation Break Frequency Equations
F LC = -------------------------------------------
f Z1 = ------------------------------------
F ESR = --------------------------------------------
f Z2 = -------------------------------------------------------
Modulator Break Frequency Equations
1
2 π x LO x CO
1
2 π x ESR x C O
(EQ. 8)
(EQ. 9)
1
2 π x R 2 x C 2
1
2 π x ( R 1 + R 3 ) x C 3
(EQ. 10)
(EQ. 11)
f P1 = ---------------------------------------------------------
2 π x R 2 x ? ---------------------- ?
f P2 = ------------------------------------
The compensation network consists of the error amplifier
(internal to the ISL6537) and the impedance networks Z IN
and Z FB . The goal of the compensation network is to provide
a closed loop transfer function with the highest 0dB crossing
frequency (f 0dB ) and adequate phase margin. Phase margin
is the difference between the closed loop phase at f 0dB and
18
1
? C 1 x C 2 ?
? C 1 + C 2 ?
1
2 π x R 3 x C 3
(EQ. 12)
(EQ. 13)
FN6516.2
December 15, 2008
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