参数资料
| 型号： | ISL8560IRZ-T |
| 厂商： | Intersil |
| 文件页数： | 14/17页 |
| 文件大小： | 0K |
| 描述： | IC REG BUCK SYNC ADJ 2A 20QFN |
| 标准包装： | 4,000 |
| 类型： | 降压（降压） |
| 输出类型： | 可调式 |
| 输出数： | 1 |
| 输出电压： | 1.21 V ~ 55 V |
| 输入电压： | 9 V ~ 60 V |
| PWM 型： | 电压模式 |
| 频率 - 开关： | 100kHz ~ 600kHz |
| 电流 - 输出： | 2A |
| 同步整流器： | 是 |
| 工作温度： | -40°C ~ 85°C |
| 安装类型： | 表面贴装 |
| 封装/外壳： | 20-VQFN 裸露焊盘 |
| 包装： | 带卷 (TR) |
| 供应商设备封装： | 20-QFN（6x6） |
ISL8560
-
operation, select bulk capacitors with voltage and current
ratings above the maximum input voltage and largest RMS
current required by the circuit. Their voltage rating should be
at least 1.25 times greater than the maximum input voltage,
while a voltage rating of 1.5 times is a conservative
guideline. For most cases, the RMS current rating
requirement for the input capacitor of a buck regulator is
approximately 1/2 the DC load current.
Δ V OSC
OSC
PWM
COMPARATOR
+
Z FB
DRIVER
DRIVER
V IN
L O
LX
C O
D
ESR
(PARASITIC)
V OUT
× ? 1 – -------------- ? + ------ × ? ----------------------------- × -------------- ? ?
V OUT ? 2 V OUT 1 ? V IN – V OUT V OUT ? 2 ?
? L × f OSC
-------------- × ? I OUT ? ?
V IN ? V IN V IN ? ?
- Z IN
ERROR
The maximum RMS current through the input capacitors
may be closely approximated through Equation 10:
MAX 12
V E/A
+
REFERENCE
AMP
DETAILED COMPENSATION COMPONENTS
(EQ. 10)
For a through hole design, several electrolytic capacitors
may be needed. For surface mount designs, solid tantalum
C 10
C 6
R 4
Z FB
C 7
Z IN
R 6
V OUT
capacitors can be used, but caution must be exercised with
regard to the capacitor surge current rating. These
COMP
R 2
capacitors must be capable of handling the surge-current at
power-up. Some capacitor series available from reputable
manufacturers are surge current tested.
ISL8560
g m -
+
FB
R 3
V OUT = 1.20 × ? 1 + ------ 2 - ?
Feedback Compensation
Figure 30 highlights the voltage-mode control loop for a
synchronous-rectified buck converter. The output voltage
(V OUT ) is regulated to the Reference voltage level. The error
amplifier output (V E/A ) is compared with the oscillator (OSC)
triangular wave to provide a pulse-width modulated (PWM)
wave with an amplitude of V IN at the LX node. The PWM
wave is smoothed by the output filter (L O and C O ).
The modulator transfer function is the small-signal transfer
function of V OUT /V E/A . This function is dominated by a DC
Gain and the output filter (L O and C O ), with a double pole
break frequency at f LC and a zero at f ESR . The DC Gain of
the modulator is simply the input voltage (V IN ) divided by the
peak-to-peak oscillator voltage Δ V OSC . The ISL8560
incorporates a feed forward loop that accounts for changes
in the input voltage. This maintains a constant modulator
gain.
Modulator Break Frequency Equations
REFERENCE
? R ?
? R 3 ?
FIGURE 30. VOLTAGE-MODE BUCK CONVERTER
COMPENSATION DESIGN AND OUTPUT
VOLTAGE SELECTION
Figure 30. Use these guidelines for locating the poles and
zeros of the compensation network:
1. Pick Gain (R 3 gm/(R 2 +R 3 ) for desired converter
bandwidth.
2. Place 1 ST Zero Below Filter’s Double Pole (~75% f LC ).
3. Place 2 ND Zero at Filter ’s Double Pole.
4. Place 1 ST Pole at the ESR Zero.
5. Place 2 ND Pole at Half the Switching Frequency.
6. Check Gain against Error transconductance’s Open-
f LC = -------------------------------------------
f ESR = --------------------------------------------
1
2 π x LO x CO
1
2 π x ESR x C O
Loop Gain.
7. Estimate Phase Margin - Repeat if Necessary.
(EQ. 11)
The compensation network consists of the transconductance
amplifier (internal to the ISL8560) and the impedance
networks Z IN and Z FB . The goal of the compensation
network is to provide a closed loop transfer function with the
highest 0dB crossing frequency (f 0dB ) and adequate phase
margin. Phase margin is the difference between the closed
loop phase at f 0dB and 180°. The equations in the following
section relate the compensation network’s poles, zeros and
gain to the components (R 2 , R 3 , R 4 , R 6 , C 10 , C 6 , and C 7 ) in
14
FN9244.7
September 19, 2008
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