参数资料
型号: ISL8560IRZ-T
厂商: Intersil
文件页数: 15/17页
文件大小: 0K
描述: IC REG BUCK SYNC ADJ 2A 20QFN
标准包装: 4,000
类型: 降压(降压)
输出类型: 可调式
输出数: 1
输出电压: 1.21 V ~ 55 V
输入电压: 9 V ~ 60 V
PWM 型: 电压模式
频率 - 开关: 100kHz ~ 600kHz
电流 - 输出: 2A
同步整流器:
工作温度: -40°C ~ 85°C
安装类型: 表面贴装
封装/外壳: 20-VQFN 裸露焊盘
包装: 带卷 (TR)
供应商设备封装: 20-QFN(6x6)
ISL8560
Compensation Break Frequency
Equations
Layout Considerations
Layout is very important in high frequency switching
f Z1 = ----------------------------------------------------------
2 π ? ---------------------------------- ? C 6
f P1 = ---------------------------
f Z2 = ---------------------------
f P2 = -----------------------------
1
( R 4 ? g m + 1 )
g m
1
2 π R 2 ? C 7
1
2 π R 6 ? C 7
1
2 π R 4 ? C 10
(EQ. 12)
converter design. With power devices switching efficiently
between 100kHz and 600kHz, the resulting current
transitions from one device to another cause voltage spikes
across the interconnecting impedances and parasitic circuit
elements. These voltage spikes can degrade efficiency,
Assumption: R6<<R2, R6<<R3, and C10<<C6.
Figure 31 shows an asymptotic plot of the DC/DC
converter ’s gain vs frequency. The actual Modulator Gain
has a high gain peak due to the high Q factor of the output
filter and is not shown in Figure 31. Using the guidelines on
page 14 should give a Compensation Gain similar to the
curve plotted. The open loop error amplifier gain bounds the
compensation gain. Check the compensation gain at F P2
with the capabilities of the error amplifier. The Closed Loop
Gain is constructed on the graph of Figure 31 by adding the
Modulator Gain (in dB) to the Compensation Gain (in dB).
This is equivalent to multiplying the modulator transfer
function to the compensation transfer function and plotting
the gain.
The compensation gain uses external impedance networks
Z FB and Z IN to provide a stable, high bandwidth (BW) overall
loop. A stable control loop has a gain crossing with
-20dB/decade slope and a phase margin greater than 45°.
Include worst case component variations when determining
phase margin.
radiate noise into the circuit, and lead to device overvoltage
stress. Careful component layout and printed circuit board
design minimizes these voltage spikes.
As an example, consider the turn-off transition of the control
MOSFET. Prior to turn-off, the MOSFET is carrying the full
load current. During turn-off, current stops flowing in the
MOSFET and is picked up by the freewheeling Schottky
diode. Any parasitic inductance in the switched current path
generates a large voltage spike during the switching interval.
Careful component selection, tight layout of the critical
components, and short, wide traces minimizes the
magnitude of voltage spikes.
There are two sets of critical components in the ISL8560
switching converter. The switching components are the most
critical because they switch large amounts of energy, and
therefore tend to generate large amounts of noise. Next are
the small signal components which connect to sensitive
nodes or supply critical bypass current and signal coupling.
V IN
VIN
100
F Z1 F Z2
F P1
F P2
C IN
80
ISL8560
60
OPEN LOOP
ERROR AMP GAIN
L
V OUT1
40
20
0
-20
-40
-60
20LOG
(R 4 /R 2 )
MODULATOR
GAIN
10 100
1k
F LC
10k
20LOG
(V IN / Δ V OSC )
F ESR
100k 1M
COMPENSATION
GAIN
CLOSED LOOP
GAIN
10M
C BP2
VCC5
PGND
LX
COMP
FB
D
C 6
R 4
R 3
C OUT1
C 10
R 2
C 7
R 6
FREQUENCY (Hz)
FIGURE 31. ASYMPTOTIC BODE PLOT OF CONVERTER GAIN
A more detailed explanation of voltage mode control of a
buck regulator can be found in Tech Brief TB417, titled
“Designing Stable Compensation Networks for Single Phase
KEY
GND PAD
ISLAND ON POWER PLANE LAYER
ISLAND ON CIRCUIT AND/OR POWER PLANE LAYER
Voltage Mode Buck Regulators.”
VIA CONNECTION TO GROUND PLANE
FIGURE 32. PRINTED CIRCUIT BOARD POWER PLANES AND
ISLANDS
15
FN9244.7
September 19, 2008
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