参数资料
| 型号： | ISL9105IRZ-T |
| 厂商： | Intersil |
| 文件页数： | 3/11页 |
| 文件大小： | 0K |
| 描述： | IC REG BUCK SYNC ADJ 0.6A 8DFN |
| 产品培训模块： | Solutions for Industrial Control Applications |
| 标准包装： | 1 |
| 类型： | 降压（降压） |
| 输出类型： | 可调式 |
| 输出数： | 1 |
| 输出电压： | 0.8 V ~ 5.5 V |
| 输入电压： | 2.7 V ~ 5.5 V |
| PWM 型： | 电流模式 |
| 频率 - 开关： | 1.6MHz |
| 电流 - 输出： | 600mA |
| 同步整流器： | 是 |
| 工作温度： | -40°C ~ 85°C |
| 安装类型： | 表面贴装 |
| 封装/外壳： | 8-VFDFN 裸露焊盘 |
| 包装： | 标准包装 |
| 供应商设备封装： | 8-DFN（2x3） |
| 产品目录页面： | 1244 (CN2011-ZH PDF) |
| 其它名称： | ISL9105IRZ-TDKR |
ISL9105
Electrical Specifications
Unless otherwise noted, all parameter limits are guaranteed over the recommended operating conditions and the
typical specifications are measured at the following conditions: T A = +25°C, V IN = 3.6V, EN = V IN , RSI = MODE =
0V, L = 3.3μH, C1 = 10μF, C2 = 10μF, I OUT = 0A (see “TYPICAL APPLICATION DIAGRAM” on page 6).
MIN
MAX
PARAMETER
SYMBOL
TEST CONDITIONS
(Note 3)
TYP
(Note 3)
UNITS
POR
Output Low Voltage
Delay Time
POR Pin Leakage Current
Minimum Supply Voltage for Valid POR Signal
Internal PGOOD Low Rising Threshold
Internal PGOOD Low Falling Threshold
Internal PGOOD High Rising Threshold
Internal PGOOD High Falling Threshold
Internal PGOOD Delay Time
Sinking 1mA, FB = 0.7V
POR = V IN = 3.6V
Percentage of nominal regulation voltage
Percentage of nominal regulation voltage
Percentage of nominal regulation voltage
Percentage of nominal regulation voltage
-
150
-
1.2
89.5
85
105.5
102
-
-
216
0.01
-
92
88
108
105
64
0.3
275
0.1
-
94.5
91
110.5
108
-
V
ms
μA
V
%
%
%
%
μs
EN, MODE, RSI
Logic Input Low
Logic Input High
-
1.4
-
-
0.4
-
V
V
Logic Input Leakage Current
Thermal Shutdown
Thermal Shutdown Hysteresis
Pulled up to 5.5V
-
-
-
0.1
150
25
1
-
-
μA
°C
°C
Pin Descriptions
VIN
Input supply voltage. Connect a 10μF ceramic capacitor to
power ground.
EN
Regulator enable pin. Enable the output when driven to high.
Shutdown the chip and discharge the output capacitor when
driven to low. Do not leave this pin floating.
POR
216ms timer output. At power-up or EN HI, this output is a
216ms delayed Power-Good signal for the output voltage.
This output can be reset by a low RSI signal. 216ms starts
when RSI goes to high.
MODE
Mode Selection pin. Connect to logic high or input voltage
VIN for low IQ mode; connect to logic low or ground for
forced PWM mode. Do not leave this pin floating.
3
PHASE
Switching node connection. Connect to one terminal of
inductor.
GND
System ground.
FB
Buck regulator output feedback. Connect to the output
through a voltage divider resistor.
RSI
This input resets the 216ms timer. When the output voltage is
within the PGOOD window, an internal timer is started and
generates a POR signal 216ms later when RSI is low. A high
RSI resets POR and RSI high to low transition restarts the
internal counter if the output voltage is within the window,
otherwise the counter is reset by the output voltage condition.
Exposed Pad
The exposed pad must be connected to the GND pin for
proper electrical performance. The exposed pad must also
be connected to as much as possible for optimal thermal
performance.
FN6415.2
March 28, 2008
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