参数资料
型号: ISL9105IRZ-T
厂商: Intersil
文件页数: 7/11页
文件大小: 0K
描述: IC REG BUCK SYNC ADJ 0.6A 8DFN
产品培训模块: Solutions for Industrial Control Applications
标准包装: 1
类型: 降压(降压)
输出类型: 可调式
输出数: 1
输出电压: 0.8 V ~ 5.5 V
输入电压: 2.7 V ~ 5.5 V
PWM 型: 电流模式
频率 - 开关: 1.6MHz
电流 - 输出: 600mA
同步整流器:
工作温度: -40°C ~ 85°C
安装类型: 表面贴装
封装/外壳: 8-VFDFN 裸露焊盘
包装: 标准包装
供应商设备封装: 8-DFN(2x3)
产品目录页面: 1244 (CN2011-ZH PDF)
其它名称: ISL9105IRZ-TDKR
ISL9105
Block Diagram
MODE
SHUTDOWN
Soft
SOFT
START
SHUTDOWN
EN
BANDGAP 0.8V
EAMP
+
OSCILLATOR
VIN
COMP
PWM/PFM
LOGIC
FB
+
Slope
SLOPE
COMP
CONTROLLER
PROTECTION
DRIVER
+
PHASE
GND
CSA1
REF4
+
+
OCP
REF1
+
REF3
+
SKIP
REF2
POR
POR
DELAY
ZERO CROSS
SENSING
RSI
Theory of Operation
REF5
SCP
+
resistance of the P-Channel MOSFET when it is turned on
The ISL9105 is a step-down switching regulator optimized
for battery-powered handheld applications. The regulator
operates at 1.6MHz fixed switching frequency under heavy
load conditions to allow small external inductor and
capacitors to be used for minimal printed-circuit board (PCB)
area. At light load, the regulator reduces the switching
frequency, unless forced to the fixed frequency, to minimize
the switching loss and to maximize the battery life. The
quiescent current when the output is not loaded is typically
only 25μA. The supply current is typically only 0.1μA when
the regulator is shut down.
PWM Control Scheme
The ISL9105 employs the current-mode pulse-width
modulation (PWM) control scheme for fast transient
response and pulse-by-pulse current limiting. Figure 15
shows the block diagram. The current loop consists of the
oscillator, the PWM comparator COMP, current sensing
circuit, and the slope compensation for the current loop
stability. The current sensing circuit consists of the
7
and the Current Sense Amplifier (CSA). The control
reference for the current loops comes from the Error
Amplifier (EAMP) of the voltage loop.
The PWM operation is initialized by the clock from the
oscillator. The P-Channel MOSFET is turned on at the
beginning of a PWM cycle and the current in the P-Channel
MOSFET starts ramping up. When the sum of the CSA output
and the compensation slope reaches the control reference of
the current loop, the PWM comparator COMP sends a signal
to the PWM logic to turn off the P-Channel MOSFET and to
turn on the N-Channel MOSFET. The N-Channel MOSFET
remains on till the end of the PWM cycle. Figure 15 shows the
typical operating waveforms during the PWM operation. The
dotted lines illustrate the sum of the compensation ramp and
the CSA output.
The output voltage is regulated by controlling the reference
voltage to the current loop. The bandgap circuit outputs a
0.8V reference voltage to the voltage control loop. The
feedback signal comes from the FB pin. The soft-start block
only affects the operation during the start-up and will be
FN6415.2
March 28, 2008
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