参数资料
| 型号： | ISL9107IRZ-T |
| 厂商： | Intersil |
| 文件页数： | 12/12页 |
| 文件大小： | 0K |
| 描述： | IC REG BUCK SYNC ADJ 1.5A 8DFN |
| 标准包装： | 6,000 |
| 类型： | 降压（降压） |
| 输出类型： | 可调式 |
| 输出数： | 1 |
| 输出电压： | 0.8 V ~ 5.5 V |
| 输入电压： | 2.7 V ~ 5.5 V |
| PWM 型： | 电流模式 |
| 频率 - 开关： | 1.6MHz |
| 电流 - 输出： | 1.5A |
| 同步整流器： | 是 |
| 工作温度： | -40°C ~ 85°C |
| 安装类型： | 表面贴装 |
| 封装/外壳： | 8-VFDFN 裸露焊盘 |
| 包装： | 带卷 (TR) |
| 供应商设备封装： | 8-DFN（2x3） |
ISL9107, ISL9108
Dual Flat No-Lead Plastic Package (DFN)
2X
L8.2x3
A
D
0.15 C A
2X
8 LEAD DUAL FLAT NO-LEAD PLASTIC PACKAGE
MILLIMETERS
0.15 C B
SYMBOL
A
MIN
0.80
NOMINAL
0.90
MAX
1.00
NOTES
-
6
INDEX
AREA
E
A1
A3
b
-
0.20
-
0.20 REF
0.25
0.05
0.32
-
-
5,8
D
2.00 BSC
-
TOP VIEW
B
D2
1.50
1.65
1.75
7,8
E
3.00 BSC
-
//
0.10
C
E2
1.65
1.80
1.90
7,8
A
0.08 C
e
0.50 BSC
-
C
SEATING
PLANE
SIDE VIEW
A3
k
L
0.20
0.30
-
0.40
-
0.50
-
8
N
8
2
(DATUM B)
D2
D2/2
7
8
Nd
4
3
Rev. 0 6/04
6
INDEX
1
2
NX k
NOTES:
1. Dimensioning and tolerancing conform to ASME Y14.5-1994.
AREA
2. N is the number of terminals.
(DATUM A)
NX L
E2/2
E2
3. Nd refers to the number of terminals on D.
4. All dimensions are in millimeters. Angles are in degrees.
5. Dimension b applies to the metallized terminal and is measured
between 0.25mm and 0.30mm from the terminal tip.
6. The configuration of the pin #1 identifier is optional, but must be
8
N N-1
e
NX b
5
located within the zone indicated. The pin #1 identifier may be
either a mold or mark feature.
7. Dimensions D2 and E2 are for the exposed pads which provide
(Nd-1)Xe
0.10
M C A B
improved electrical and thermal performance.
NX (b)
5
SECTION "C-C"
REF.
BOTTOM VIEW
(A1)
C C
CL
L
TERMINAL TIP
8. Nominal dimensions are provided to assist with PCB Land
Pattern Design efforts, see Intersil Technical Brief TB389.
e
FOR EVEN TERMINAL/SIDE
All Intersil U.S. products are manufactured, assembled and tested utilizing ISO9000 quality systems.
Intersil Corporation’s quality certifications can be viewed at www.intersil.com/design/quality
Intersil products are sold by description only. Intersil Corporation reserves the right to make changes in circuit design, software and/or specifications at any time without
notice. Accordingly, the reader is cautioned to verify that data sheets are current before placing orders. Information furnished by Intersil is believed to be accurate and
reliable. However, no responsibility is assumed by Intersil or its subsidiaries for its use; nor for any infringements of patents or other rights of third parties which may result
from its use. No license is granted by implication or otherwise under any patent or patent rights of Intersil or its subsidiaries.
For information regarding Intersil Corporation and its products, see www.intersil.com
12
FN6612.0
December 21, 2007
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