参数资料
| 型号： | ISL9107IRZ-T |
| 厂商： | Intersil |
| 文件页数： | 3/12页 |
| 文件大小： | 0K |
| 描述： | IC REG BUCK SYNC ADJ 1.5A 8DFN |
| 标准包装： | 6,000 |
| 类型： | 降压（降压） |
| 输出类型： | 可调式 |
| 输出数： | 1 |
| 输出电压： | 0.8 V ~ 5.5 V |
| 输入电压： | 2.7 V ~ 5.5 V |
| PWM 型： | 电流模式 |
| 频率 - 开关： | 1.6MHz |
| 电流 - 输出： | 1.5A |
| 同步整流器： | 是 |
| 工作温度： | -40°C ~ 85°C |
| 安装类型： | 表面贴装 |
| 封装/外壳： | 8-VFDFN 裸露焊盘 |
| 包装： | 带卷 (TR) |
| 供应商设备封装： | 8-DFN（2x3） |
ISL9107, ISL9108
Electrical Specifications
Unless otherwise noted, all parameter limits are guaranteed over the recommended operating conditions and
the typical specifications are measured at the following conditions: T A = +25°C, V IN = V EN = 3.6V, L = 2.2μH,
C 1 = 10μF, C 2 = 10μF, I OUT = 0A (see the Typical Application Circuit on page 7). (Continued)
PARAMETER
SYMBOL
TEST CONDITIONS
MIN
TYP
MAX
UNITS
PG (NOTE 1)
Output Low Voltage
Delay Time
PG Pin Leakage Current
Minimum Supply Voltage for Valid PG Signal
Internal PGOOD Low Rising Threshold
Internal PGOOD Low Falling Threshold
Internal PGOOD High Rising Threshold
Internal PGOOD High Falling Threshold
Internal PGOOD Delay Time
Sinking 1mA, VFB = 0.7V
PG = V IN = 3.6V
Percentage of Nominal Regulation Voltage
Percentage of Nominal Regulation Voltage
Percentage of Nominal Regulation Voltage
Percentage of Nominal Regulation Voltage
-
150
-
1.2
89.5
85
108.2
104
-
-
215
0.01
-
92
88
110.7
107
50
0.3
275
0.1
-
94.5
91
113.2
110
-
V
ms
μA
V
%
%
%
%
μs
RSI (NOTE 1), EN, MODE
Logic Input Low
Logic Input High
-
1.4
-
-
0.4
-
V
V
Logic Input Leakage Current
Thermal Shutdown
Thermal Shutdown Hysteresis
Pulled up to 5.5V
-
-
-
0.1
150
25
1
-
-
μA
°C
°C
Pin Descriptions
ISL9107
ISL9108
PIN #
1
2
4
6
7
8
E-PAD
PIN NAME PIN NAME
VIN
EN
MODE
FB
GND
SW
-
DESCRIPTION
Input supply voltage pin. Connect a 10μF ceramic capacitor to power ground .
Enable pin. Enable the output when driven to high. Shut down the chip and discharge output capacitor when
driven to low. Do not leave this pin floating.
Mode selection pin. Connect to logic high or VIN to enable skip mode; connect to logic low or ground for force
PWM mode.
Buck regulator output feedback pin. Connect to the output voltage through voltage divider resistors for
adjustable output voltage.
System ground.
Switching node pin. Connect to one terminal of the inductor.
Exposed pad. It should be connected to ground for proper electrical performance. The exposed pad must also
be connected to as much as possible for optimal thermal performance.
3
PG
NC
For ISL9107, it is 215ms timer output. It outputs 215ms delayed power-good signal when output voltage is
within power-good window. It can be reset by a high RSI signal, then 215ms starts when RSI goes from high
to low.
For ISL9108, do not connect. Leave this pin floating.
5
RSI
NC
For ISL9107, this input resets the 215ms timer. Please refer to “Theory of Operation” on page 9 for more
details.
For ISL9108, do not connect. Leave this pin floating.
3
FN6612.0
December 21, 2007
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