参数资料
型号: ISL95870BHRZ-T
厂商: Intersil
文件页数: 26/28页
文件大小: 0K
描述: IC CTRLR PWM 1PHASE GPU 20QFN
标准包装: 6,000
应用: 控制器,GPU 内核电源
输入电压: 3.3 V ~ 25 V
输出数: 1
输出电压: 0.5 V ~ 5 V
工作温度: -10°C ~ 100°C
安装类型: 表面贴装
封装/外壳: 20-VFQFN 裸露焊盘
供应商设备封装: 20-QFN(3x4)
包装: 带卷 (TR)
ISL95870, ISL95870A, ISL95870B
Ultra Thin Quad Flat No-Lead Plastic Package (UTQFN)
D
A
B
L16.2.6x1.8A
16 LEAD ULTRA THIN QUAD FLAT NO-LEAD PLASTIC
PACKAGE
6
INDEX AREA
N
E
MILLIMETERS
2X
2X
0.10 C
0.10 C
1 2
SYMBOL
A
A1
MIN
0.45
-
NOMINAL
0.50
-
MAX
0.55
0.05
NOTES
-
-
TOP VIEW
A3
0.127 REF
-
b
0.15
0.20
0.25
5
0.10 C
0.05 C
A
C
D
E
2.55
1.75
2.60
1.80
2.65
1.85
-
-
SEATING PLANE
A1
e
0.40 BSC
-
SIDE VIEW
K
L
L1
0.15
0.35
0.45
-
0.40
0.50
-
0.45
0.55
-
-
-
PIN #1 ID
L1
e
1 2
K
NX L
N
Nd
Ne
16
4
4
2
3
3
(DATUM B)
(DATUM A)
BOTTOM VIEW
CL
NX b 5
16X
0.10 M C A B
0.05 M C
θ 0 - 12 4
Rev. 5 2/09
NOTES:
1. Dimensioning and tolerancing conform to ASME Y14.5-1994.
2. N is the number of terminals.
3. Nd and Ne refer to the number of terminals on D and E side,
respectively.
4. All dimensions are in millimeters. Angles are in degrees.
5. Dimension b applies to the metallized terminal and is measured
NX (b)
5
(A1)
L
between 0.15mm and 0.30mm from the terminal tip.
6. The configuration of the pin #1 identifier is optional, but must be
located within the zone indicated. The pin #1 identifier may be
SECTION "C-C"
C C
e
TERMINAL TIP
either a mold or mark feature.
7. Maximum package warpage is 0.05mm.
8. Maximum allowable burrs is 0.076mm in all directions.
9. JEDEC Reference MO-255.
10. For additional information, to assist with the PCB Land Pattern
Design effort, see Intersil Technical Brief TB389.
3.00
1.80
1.40
1.40
2.20
0.90
0.40
0.50
0.20
0.40
0.20
10 LAND PATTERN
26
FN6899.1
December 2, 2013
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