参数资料
| 型号： | ISL97649AIRZ |
| 厂商： | Intersil |
| 文件页数： | 12/21页 |
| 文件大小： | 0K |
| 描述： | IC POWER MANAGEMENT |
| 标准包装： | 75 |
| 系列： | * |
ISL97649A
TABLE 2. BOOST CONVERTER INDUCTOR RECOMMENDATION
The efficiency of the LDO depends on the difference between
INDUCTOR
DIMENSIONS
(mm)
MFG
PART
NUMBER
NOTE
input voltage and output voltage (Equation 7) by assuming LDO
quiescent current is much lower than LDO output current:
? V LDO_IN ?
10μH/
2.2Apeak
6.6x7.3x1.2
Cyntec PCME061B-100MS
PCB
space/profile
optimization
η ( % ) = ? ------------------------------ ? × 100%
? V LDO_OUT ?
(EQ. 7)
TABLE 3. BOOST CONVERTER RECTIFIER DIODE RECOMMENDATION
The less difference between input and output voltage, the higher
efficiency it is.
DIODE
PMEG2010ER
MSS1P2U
V R /I AVG RATING
20V/1A
20V/1A
PACKAGE
SOD123W NXP
MicroSMP VISHAY
MFG
Ceramic capacitors are recommended for the LDO input and
output capacitors. Intersil recommends an output capacitor
within the 1μF to 4.7μF range and a maximum feedback resistor
impedance of 20k ? . Larger capacitors help to reduce noise and
Output Capacitor
The output capacitor supplies the load directly and reduces the
ripple voltage at the output. Output ripple voltage consists of two
deviation during transient load change. Some capacitors are
recommended in Table 5.
TABLE 5. LDO OUTPUT CAPACITOR RECOMMENDATION
components:
CAPACITOR
SIZE
MFG
PART NUMBER
V RIPPLE = I LPK × ESR + ------------------------ × ---------------- × ----
V O – V IN I O 1
V C f
1. The voltage drop due to the inductor ripple current flowing
through the ESR of the output capacitor.
2. Charging and discharging of the output capacitor.
(EQ. 6)
O OUT s
1μF/10V 0603
1μF/6.3V 0603
2.2μF/6.3V 0603
Supply Monitor Circuit
TDK
MURATA
TDK
C1608X7R1A105K
GRM188R70J105K
C1608X7R0J225K
For low ESR ceramic capacitors, the output ripple is dominated
by the charging and discharging of the output capacitor. The
voltage rating of the output capacitor should be greater than the
maximum output voltage.
Note: Capacitors have a voltage coefficient that makes their
effective capacitance drop as the voltage across them increases.
C OUT in Equation 6 assumes the effective value of the capacitor
at a particular voltage and not the manufacturer’s stated value,
measured at 0V.
The Supply Monitor circuit monitors the voltage on VDIV, and sets
open-drain output RESET low when VDIV is below 1.28V (rising)
or 1.22V (falling).
There is a delay on the rising edge, controlled by a capacitor on
CD2. When VDIV exceeds 1.28V (rising), CD2 is charged up from
0V to 1.217V by a 10μA current source. Once CD2 exceeds
1.217V, RESET will go tri-state. When VDIV falls below 1.22V,
RESET will become low with a 650 ? pull-down resistance. The
delay time is controlled by Equation 8:
Table 4 shows some selections of output capacitors.
t delay = 121.7k × CD2
(EQ. 8)
TABLE 4. BOOST OUTPUT CAPACITOR RECOMMENDATION
CAPACITOR SIZE MFG PART NUMBER
10μF/25V 1210 TDK C3225X7R1E106M
For example, the delay time is 12.17ms if the CD2 = 100nF.
Figure 13 shows the Supply Monitor Circuit timing diagram.
10μF/25V
1210
Murata
GRM32DR61E106K
Compensation
1.28V
The boost converter of ISL97649A can be compensated by an RC
network connected from the COMP pin to ground. 15nF and 5.5k
RC network is used in the demo board. The larger value resistor
and lower value capacitor can lower the transient overshoot,
however, at the expense of the stability of the loop.
Linear Regulator (LDO)
The ISL97649A includes an LDO with adjustable output. It can
VDIV
CD2
1.217V
RESET DELAY TIME IS
1.22V
supply current up to 350mA. The output voltage is adjusted by
connection of the ADJ pin.
RESET
CONTROLLED BY CD2
CAPACITOR
FIGURE 13. SUPPLY MONITOR CIRCUIT TIMING DIAGRAM
12
FN7928.3
June 27, 2013
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