参数资料
| 型号： | ISL97649AIRZ |
| 厂商： | Intersil |
| 文件页数： | 7/21页 |
| 文件大小： | 0K |
| 描述： | IC POWER MANAGEMENT |
| 标准包装： | 75 |
| 系列： | * |
ISL97649A
Electrical Specifications VIN = ENABLE = 3.3V, AVDD = 8V, VLDO = 2.5V, VON = 24V, VOFF = - 6V. Boldface limits apply over the
operating temperature range, -40°C to +85°C. (Continued)
MIN
TYP
MAX
SYMBOL
I SC
PARAMETER
Output Short Circuit Current
Pull-up
TEST CONDITIONS
(Note 6)
150
(Note 7)
225
(Note 6)
UNITS
mA
Pull-down
150
200
mA
SR
Slew Rate
25
V/μs
BW
Gain Bandwidth
-3dB gain point
20
MHz
DIGITAL CONTROLLED POTENTIOMETER
SET VR
(Note 12)
SET Voltage Resolution
8
Bits
SET DNL
(Note 8, 9,
SET Differential Nonlinearity
T A = +25°C
±1
LSB
14)
SET ZSE
(Note 10, 14)
SET FSE
(Note 11,14)
I RSET
SET Zero-Scale Error
SET Full-Scale Error
RSET Current
T A = +25°C
T A = +25°C
±2
±8
100
LSB
LSB
μA
AVDD to SET AVDD to SET Voltage Attenuation
FAULT DETECTION THRESHOLD
1:20
V/V
V UVLO
OVP AVDD
(Note 13)
T OFF
Undervoltage Lock out Threshold
Boost Overvoltage Protection Off
Threshold to Shutdown IC
Thermal Shut-Down all Channels
PV IN rising
PV IN falling
Temperature rising
2.25
2.125
15.0
2.33
2.20
15.5
153
2.41
2.27
16.0
V
V
V
°C
POWER SEQUENCE TIMING
t ss VLOGIC
VLOGIC Soft-start Time
0.45
ms
I ss
Boost Soft-start Current
3
5.5
8
μA
Serial Interface Specifications
For SCL and SDA Unless Otherwise Noted.
MIN
TYP
MAX
SYMBOL
PARAMETER
TEST CONDITIONS
(Note 14)
(Note 7)
(Note 14)
UNITS
f SCL
(Note 6)
SCL Frequency
400
kHz
t iN
(Note 6)
t AA
t BUF
t LOW
t HIGH
t SU:STA
t HD:STA
Pulse Width Suppression Time at SDA
and SCL Inputs
SCL Falling Edge to SDA Output Data
Valid
Time the Bus Must be Free Before the
Start of a New Transmission
Clock LOW Time
Clock HIGH Time
START Condition Set-up Time
START Condition Hold Time
Any pulse narrower than the max spec is
suppressed
SCL falling edge crossing 30% of V IN , until
SDA exits the 30% to 70% of V IN window
SDA crossing 70% of V CC during a STOP
condition, to SDA crossing 70% of V IN during
the following START condition
Measured at the 30% of V IN crossing
Measured at the 70% of V IN crossing
SCL rising edge to SDA falling edge; both
crossing 70% of V IN
From SDA falling edge crossing 30% of V IN to
SCL falling edge crossing 70% of V IN
480
480
400
480
400
50
480
ns
ns
ns
ns
ns
ns
ns
7
FN7928.3
June 27, 2013
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