参数资料
| 型号： | ISL97651ARTZ-T |
| 厂商： | Intersil |
| 文件页数： | 16/19页 |
| 文件大小： | 0K |
| 描述： | IC LCD SUPPLY HP 4CHN 36-TQFN |
| 标准包装： | 4,000 |
| 应用： | LCD 电视机/监控器 |
| 电流 - 电源： | 400µA |
| 电源电压： | 4 V ~ 5.5 V |
| 工作温度： | -40°C ~ 105°C |
| 安装类型： | 表面贴装 |
| 封装/外壳： | 36-WFQFN 裸露焊盘 |
| 供应商设备封装： | 36-TQFN 裸露焊盘（6x6） |
| 包装： | 带卷 (TR) |
ISL97651
V REF
C19
A2
VDD
VSUP
100pF
FAULT
0.4V
FBN
C20
820pF
R6
40k
A1
0.2V
R7
328k
1.2MHz
STOP
M2
CLK
NOUT
C12
220nF
D2
V OFF (-8V)
D3
C13
470nF
EN
PWM
CONTROL
M1
PGND
FIGURE 14. NEGATIVE CHARGE PUMP BLOCK DIAGRAM
V ON Slice Circuit
The V ON Slice Circuit functions as a three way multiplexer,
switching the voltage on COM between ground, DRN and SRC,
under control of the start-up sequence and the CTL pin.
During the start-up sequence, COM is held at ground via an
NDMOS FET, with ~1k impedance. Once the start-up
sequence has completed, CTL is enabled and acts as a
multiplexer control such that if CTL is low, COM connects to
DRN through a 30 Ω internal MOSFET, and if CTL is high,
COM connects to P OUT internally via a 5 Ω MOSFET.
The slew rate of start-up of the switch control circuit is mainly
restricted by the load capacitance at COM pin as
Equation 21:
Start-Up Sequence
Figure 15 shows a detailed start up sequence waveform. For
a successful power up, there should be 6 peaks at V CDLY .
When a fault is detected, the device will latch off until either
EN is toggled or the input supply is recycled.
When the input is higher than 2.75V; if either EN or ENL is H,
V REF turns on. If ENL is H, V LOGIC turns on. If EN is H, an
internal current source starts to charge C CDLY to an upper
threshold using a fast ramp followed by a slow ramp. Several
more ramps follow, during which time the device checks for
fault conditions. If a fault is found, the sequence is halted.
Initially the boost is not enabled so A VDD rises to
V IN - V DIODE through the output diode. Hence, there is a step
Δ V -
V g
( R i || R L ) × C L
Δ t
------- = -------------------------------------
(EQ. 21)
at A VDD during this part of the start up sequence. If this step is
not desirable, an external PMOS FET can be used to delay
the output until the boost is enabled internally. The delayed
V DRN = ---------------------------------------------------------------
RWhere V g is the supply voltage applied to DRN or voltage
at P OUT , which range is from 0V to 36V. R i is the resistance
between COM and DRN or P OUT including the internal
MOSFET r DS(On) , the trace resistance and the resistor
inserted, R L is the load resistance of switch control circuit,
and C L is the load capacitance of switch control circuit.
In the “Typical Application Diagram” on page 10, R10, R11
and C15 give the bias to DRN based on Equation 22:
V ON ? R 11 +AVDD ? R 10
R 10 + R 11 (EQ. 22)
And R12 can be adjusted to adjust the slew rate.
16
output appears at A VDD .
A VDD soft-starts at the beginning of the third ramp. The soft-
start ramp depends on the value of the C DLY capacitor. The
range of C DLY capacitor value is from 10nF to 220nF. For
C DLY of 220nF, the soft-start time is ~8ms.
V OFF turns on at the start of the fourth peak, at the same time
DELB gate goes low to turn on the external PMOS to
generate a delayed A VDD output.
V ON is enabled at the beginning of the sixth ramp.
Once the start-up sequence is complete, the voltage on the
C DLY capacitor remains at 1.15V until either a fault is detected
or the EN pin is disabled. If a fault is detected, the voltage on
C DLY rises to 2.4V at which point the chip is disabled until the
power is cycled or enable is toggled.
FN7493.3
April 24, 2009
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