参数资料
型号: ISL97652IRZ-T
厂商: Intersil
文件页数: 17/25页
文件大小: 0K
描述: IC LCD SUPPLY 4CH DUAL AMP 48QFN
标准包装: 4,000
应用: LCD 电视机/监控器
电流 - 电源: 500µA
电源电压: 8 V ~ 15 V
工作温度: -40°C ~ 85°C
安装类型: 表面贴装
封装/外壳: 48-VFQFN 裸露焊盘
供应商设备封装: 48-QFN(7x7)
包装: 带卷 (TR)
ISL97652
V REF
C3
A2
VDC
V SUP
100pF
FAULT
0.53V
FBN
C2
820pF
R5
40.2k
A1
0.5V
R6
453k
F OSC
STOP
M2
CLK
DRVN
C N
0.1μF
D4
V OFF (-8V)
D3
C OFF
EN
PWM
CONTROL
M1
1μF
GND
FIGURE 19. NEGATIVE CHARGE PUMP BLOCK DIAGRAM
The maximum V OFF output voltage of a single stage charge pump is:
V OFF_MAX ( 2x ) = – V SUP + V DIODE + 2 ? I OUT ? ( R ON ( NOUT ) H + R ON ( NOUT ) L )
(EQ. 18)
R5 and R6 in the Typical Application Diagram determine
V OFF output voltage.
(without the boost running) is large enough to satisfy the
regulated VOFF supply.
V OFF = V FBN ? ? 1 + -------- ? – V REF ? ? -------- ?
R6 R6
? R5 ? ? R5 ?
(EQ. 19)
Improving Charge Pump Noise Immunity
Depending on PCB layout and environment, noise pick-up at
Charge Pump Supply
The magnitude of the SUP supply will determine the charge
pump diode configuration; whether x2 or x3 for the positive
charge pump or x1 or x2 for the negative charge pump.
An independent charge pump supply pin 13 (SUP) is
provided and this may be connected to Vin, Vmain, AVDD or
some other suitable supply.
Note that if AVDD is chosen for the SUP supply, then a
potential fault-like interaction with the supply sequencing
and fault checking is present; when EN1 goes high (with
EN2 low), fault checking on the VOFF charge pump is
started by the voltage ramp on DEL1. If this pin reaches
~1.9V before VOFF is within 90% of it's regulation voltage
then the buck converter (Tcon bias) and Voff will be
continually re-started. This condition will arise if the SUP
supply has not been activated by EN2 going high before
DEL1 has reached 1.9V. One solution would be to increase
the capacitance on DEL1 to overlap enough in time with the
EN2 going high. This does have the disadvantage of
lengthening the fault detection time of the VOFF charge
pump under true fault conditions and it also lengthens the
initial VOFF turn-on time. Another solution would be to
supply SUP from Vmain as long as the magnitude of Vmain
17
the FBP and FBN inputs, which may degrade load regulation
performance, can be reduced by the inclusion of capacitors
across the feedback resistors (e.g. in the Application
Diagram, C4 and C5 for the positive charge pump).
Set R7 ? C4 = R8 ? C5 with C4 ~ 100pF.
V ON-SLICE Circuit Operation
The Von slice circuit functions as a three way multiplexer,
switching VGHM between ground, VGL and VGH (typ 15-
30V). Voltage selection is provided by digital inputs VDPM
(enable) and VFLK (control). HIGH to LOW delay and slew
control is provided by external components on pins CE and
RE respectively. The block diagram of the VON-SLICE
circuit is shown in Figure 3.
When VDPM is LOW, the block is disabled and VGHM is
grounded.
When VDPM is HIGH, VGHM is determined by VFLK; when
VFLK goes LOW, there is a delay controlled by the capacitor
attached to the CE pin, following which VGHM is driven to
VGL, with a slew rate controlled by the resistor attached to
the RE pin. Note that VGL is used only as a reference
voltage for an amplifier, thus does not have to source or sink
a significant DC current. When VFLK goes HIGH, VGHM is
FN9287.1
November 2, 2007
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ISL97653IRZ 制造商:Intersil Corporation 功能描述: