参数资料
型号: ISL97652IRZ
厂商: Intersil
文件页数: 19/25页
文件大小: 0K
描述: IC LCD SUPPLY HP 4CHN 48-QFN
标准包装: 43
应用: LCD 电视机/监控器
电流 - 电源: 500µA
电源电压: 8 V ~ 15 V
工作温度: -40°C ~ 85°C
安装类型: 表面贴装
封装/外壳: 48-VFQFN 裸露焊盘
供应商设备封装: 48-QFN(7x7)
包装: 管件
ISL97652
VGH
VGHM
SLOPE CONTROLLED
VFLK
VGL
0
BY RE AND LOAD
CAPACITANCE
t
0
T CE
t
DELAY TIME CONTROLLED BY CE
~1.94V
CE
~1.265V
0
FIGURE 21. VON-SLICE TIMING WAVEFORM
t
High Performance V COM Amplifiers
The integrated high performance amplifiers are designed to
drive the V COM plane in TFT-LCD displays. Under normal
operational conditions, the amplifiers are permanently
enabled when the AVIN supply is present. Under fault
conditions and with EN1 active, the temperature shut-down
charge. Once the threshold is reached, the negative charge
pump will begin. Removing the DLY1 capacitor will cause the
negative charge pump to start immediately once the buck
regulator reaches 90% of the target value. The delay time
and soft-start times are determined using the following
equations:
T DLY1 = C DL1 × --------------
T SSB = C SSB × ---------------
I
(T OFF exceeded) will disable the amplifiers until the
temperature drops to T ON . Temperature shut-down of the
amplifiers is disabled if EN1 is disabled.
The amplifiers integrated in to the ISL97652 feature high
output current of 50mA minimum and high slew rate of
V DL1
I DL1
V SSB
SSB
(EQ. 20)
(EQ. 21)
50V/μs. Both inputs and outputs have rail-to-rail capability.
Start-Up Sequence Control
The ISL97652 features extensive start-up sequence control
options. Two enable pins and two delay control pins are
used to set the start-up sequence.
The EN1 enable pin controls the buck regulator and negative
charge pump controller. When EN1 goes H, the internal 5.3V
regulator starts up. Once the regulator output on pin 27
(VDC) exceeds it's UVLO threshold, the REF pin starts to
charge up to the normal output level. Once REF is within
15% of it's final value, the buck regulator will start to operate.
Note that if V REF moves more than 15% from it's target
The EN2 pin is used to control the boost and positive charge
pump circuits.Note that EN2 is ignored until the buck
converter has reached 90% of it's target value. When taken
high, the internal PFET is turned on to connect the input to
the A VDD output. A capacitor connected to SUI provides
control over the soft connect to limit inrush current. Next, the
boost converter starts to operate. The soft-start time for the
boost is set using the capacitor tied to the SS pin. Once the
output reaches 90% of the target value, the DLY2 timer
starts. Once completed, the positive V ON charge pump
starts to operate. If CDL2 is not present, the V ON charge
pump will start immediately once the boost is in regulation.
The delay time is determined using the following equation:
T DLY2 = C DL2 × --------------
I
T SS = C SS × -----------
I
value, all major functions will be disabled until REF returns to
it's normal range. This involves the chip going through the
normal start-up sequence from buck start-up onwards,
depending on the state of the enable signals EN1, EN2. The
soft-start time is set using the capacitor connected to SSB.
Once the output reaches 90% the DLY1 capacitor begins to
19
V DL2
DL2
V SS
SS
(EQ. 22)
(EQ. 23)
FN9287.1
November 2, 2007
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