参数资料
| 型号： | ISLA212P20IRZ |
| 厂商： | Intersil |
| 文件页数： | 15/36页 |
| 文件大小： | 0K |
| 描述： | IC ADC 12BIT SRL/SPI 72QFN |
| 标准包装： | 1 |
| 系列： | FemtoCharge™ |
| 位数： | 12 |
| 采样率（每秒）： | 200M |
| 数据接口： | 串行，SPI? |
| 转换器数目： | 1 |
| 功率耗散（最大）： | 468mW |
| 电压电源： | 模拟和数字 |
| 工作温度： | -40°C ~ 85°C |
| 安装类型： | 表面贴装 |
| 封装/外壳： | 72-VFQFN 裸露焊盘 |
| 供应商设备封装： | 72-QFN（10x10） |
| 包装： | 托盘 |
| 输入数目和类型： | * |
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ISLA212P
22
FN7717.2
November 30, 2012
Data Format
Output data can be presented in three formats: two’s
complement (default), Gray code and offset binary. The data
format can be controlled through the SPI port, by writing to
address 0x73. Details on this are contained in “Serial Peripheral
Offset binary coding maps the most negative input voltage to
code 0x000 (all zeros) and the most positive input to 0xFFF (all
ones). Two’s complement coding simply complements the MSB
of the offset binary representation.
When calculating Gray code the MSB is unchanged. The
remaining bits are computed as the XOR of the current bit
position and the next most significant bit. Figure 33 shows this
operation.
Converting back to offset binary from Gray code must be done
recursively, using the result of each bit for the next lower bit as
shown in Figure 34.
Mapping of the input voltage to the various data formats is
shown in Table 3.
Clock Divider Synchronous Reset
If the selectable clock divider is used, the ADC's internal sample
clock will be at half the frequency (DIV=2) or one quarter the
frequency (DIV=4) of the device clock. The phase relationship
between the sample clock and the device clock is initially
indeterminate. An output clock (CLKOUTP, CLKOUTN) is provided
to facilitate latching of the sampled data and estimation of the
internal sample clock's phase. The output clock has a fixed
phase relationship to the sample clock. When the selectable
clock divider is set to 2 or 4, the output clock's phase relationship
to the sample clock remains fixed but is initially indeterminate
with respect to the device clock. When the selectable clock
divider is set to 2 or 4, the synchronous clock divider reset
feature allows the phase of the internal sample clock and the
output clock to be synchronized (refer to Figure 35) with respect
to the device clock. This simplifies data capture in systems
employing multiple A/Ds where sampling of the inputs is desired
to be synchronous.
The reset signal must be well-timed with respect to the sample
clock (See “Switching Specifications” on page 13).
A 100
Ω differential termination resistor must be supplied
between CLKDIVRSTP and CLKDIVRSTN, external to the ADC, (on
the PCB) and should be located as close to the CLKDIVRSTP/N
pins as possible.
FIGURE 33. BINARY TO GRAY CODE CONVERSION
10
11
9
0
1
BINARY
10
11
9
0
GRAY CODE
1
FIGURE 34. GRAY CODE TO BINARY CONVERSION
10
11
9
0
1
BINARY
10
11
9
0
GRAY CODE
1
TABLE 3. INPUT VOLTAGE TO OUTPUT CODE MAPPING
INPUT
VOLTAGE
OFFSET BINARY
TWO’S
COMPLEMENT
GRAY CODE
–Full Scale
0000 0000 0000
1000 0000 0000
0000 0000 0000
–Full Scale
+ 1LSB
0000 0000 0001
1000 0000 0001
0000 0000 0001
Mid–Scale
1000 0000 0000
0000 0000 0000
1100 0000 0000
+Full Scale
– 1LSB
1111 1111 1110
0111 1111 1110
1000 0000 0001
+Full Scale
1111 1111 1111
0111 1111 1111
1000 0000 0000
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