参数资料
| 型号： | ISLA212P20IRZ |
| 厂商： | Intersil |
| 文件页数： | 9/36页 |
| 文件大小： | 0K |
| 描述： | IC ADC 12BIT SRL/SPI 72QFN |
| 标准包装： | 1 |
| 系列： | FemtoCharge™ |
| 位数： | 12 |
| 采样率（每秒）： | 200M |
| 数据接口： | 串行，SPI? |
| 转换器数目： | 1 |
| 功率耗散（最大）： | 468mW |
| 电压电源： | 模拟和数字 |
| 工作温度： | -40°C ~ 85°C |
| 安装类型： | 表面贴装 |
| 封装/外壳： | 72-VFQFN 裸露焊盘 |
| 供应商设备封装： | 72-QFN（10x10） |
| 包装： | 托盘 |
| 输入数目和类型： | * |
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ISLA212P
17
FN7717.2
November 30, 2012
Theory of Operation
Functional Description
The ISLA212P is based on a 12-bit, 250MSPS A/D converter core
that utilizes a pipelined successive approximation architecture
(see Figure 19). The input voltage is captured by a Sample-Hold
Amplifier (SHA) and converted to a unit of charge. Proprietary
charge-domain techniques are used to successively compare the
input to a series of reference charges. Decisions made during the
successive approximation operations determine the digital code
for each input value. Digital error correction is also applied,
resulting in a total latency of 10 clock cycles. This is evident to the
user as a latency between the start of a conversion and the data
being available on the digital outputs.
Power-On Calibration
As mentioned previously, the cores perform a self-calibration at
start-up. An internal power-on-reset (POR) circuit detects the
supply voltage ramps and initiates the calibration when the
analog and digital supply voltages are above a threshold. The
following conditions must be adhered to for the power-on
calibration to execute successfully.
A frequency-stable conversion clock must be applied to the
CLKP/CLKN pins.
DNC pins must not be connected.
SDO has an internal pull-up and should not be driven
externally.
RESETN is pulled low by the ADC internally during POR.
External driving of RESETN is optional.
SPI communications must not be attempted.
A user-initiated reset can subsequently be invoked if these
conditions cannot be met at power-up.
After the power supply has stabilized, the internal POR releases
RESETN, and an internal pull-up pulls it high, which starts the
calibration sequence. If a subsequent user-initiated reset is
desired, the RESETN pin should be connected to an open-drain
driver with an off-state/high impedance state leakage of less
than 0.5mA. This assures exit from the reset state so calibration
can start.
The calibration sequence is initiated on the rising edge of
RESETN, as shown in Figure 20. Calibration status can be
determined by reading the cal_status bit (LSB) at 0xB6. This bit is
‘0’ during calibration and goes to a logic ‘1’ when calibration is
complete. The data outputs produce 0xCCCC during calibration;
this can also be used to determine calibration status.
If the selectable clock divider is set to 1 (default), the output
clock (CLKOUTP/CLKOUTN) will not be affected by the assertion
of RESETN. If the selectable clock divider is set to 2 or 4, the
output clock is set low while RESETN is asserted (low). Normal
operation of the output clock resumes at the next input clock
edge (CLKP/CLKN) after RESETN is de-asserted. At 250MSPS the
nominal calibration time is 200ms, while the maximum
calibration time is 550ms.
FIGURE 17. TWO-TONE SPECTRUM (F1 = 70MHz, F2 = 71MHz AT
-7dBFS)
FIGURE 18. TWO-TONE SPECTRUM (F1 = 170MHz, F2 = 171MHz AT
-7dBFS)
Typical Performance Curves
All Typical Performance Characteristics apply under the following conditions unless otherwise noted: AVDD = OVDD = 1.8V, TA = +25°C,
AIN =-1dBFS, fIN = 105MHz, fSAMPLE = 250MSPS. (Continued)
0
20
40
60
80
100
120
-120
-100
-80
-60
-40
-20
0
FREQUENCY (MHz)
AMPLIT
UDE
(dBFS)
IMD2
IMD3
2ND HARMONICS
3RD HARMONICS
IMD3 = -87 dBFS
Filename
Core fs (MHz)
-120
-100
-80
-60
-40
-20
0
AMPLITUDE
(dBFS)
IMD3 = -97 dBFS
0
20
40
60
80
100
120
FREQUENCY (MHz)
IMD2
IMD3
2ND HARMONICS
3RD HARMONICS
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相关代理商/技术参数 |
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|---|---|
| ISLA212P25 | 制造商:INTERSIL 制造商全称:Intersil Corporation 功能描述:12-Bit, 500MSPS ADC Programmable Built-in Test Patterns |
| ISLA212P25IRZ | 制造商:Intersil Corporation 功能描述:12-BIT 250MSPS ADC, 72-PIN QFN - Trays 制造商:Intersil Corporation 功能描述:IC ADC 12BIT SPI/SRL 250M 72QFN |
| ISLA212P50 | 制造商:INTERSIL 制造商全称:Intersil Corporation 功能描述:12-Bit, 500MSPS ADC Programmable Built-in Test Patterns |
| ISLA212P50_1105 | 制造商:INTERSIL 制造商全称:Intersil Corporation 功能描述:12-Bit, 500MSPS ADC Programmable Built-in Test Patterns |
| ISLA212P50IRZ | 制造商:Intersil Corporation 功能描述:12-BIT 500MSPS ADC, 72-PIN QFN - Bulk 制造商:Intersil 功能描述:Intersil ISLA212P50IRZ Analog to Digital Converters (ADC) 制造商:Intersil Corporation 功能描述:IC ADC 12BIT SRL/SPI 72QFN 制造商:Intersil 功能描述:12-BIT 500MSPS ADC 7 2-PIN |
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