参数资料
型号: ISO7221AQDRQ1
厂商: Texas Instruments
文件页数: 7/24页
文件大小: 0K
描述: IC DGTL ISOLATOR 1MBPS DL 8SOIC
标准包装: 1
输入 - 1 侧/2 侧: 1/1
通道数: 2
电源电压: 3 V ~ 5.5 V
电压 - 隔离: 2500Vrms
数据速率: 1Mbps
传输延迟: 410ns
输出类型: CMOS
封装/外壳: 8-SOIC(0.154",3.90mm 宽)
供应商设备封装: 8-SOIC
包装: 标准包装
工作温度: -40°C ~ 125°C
其它名称: 296-27336-6

ISO7220A-Q1
ISO7221A-Q1
ISO7221C-Q1
www.ti.com
ELECTRICAL CHARACTERISTICS
V CC1 = V CC2 = 3.3 V (1) , over recommended operating conditions (unless otherwise noted)
SLLS965C – JULY 2009 – REVISED MAY 2012
PARAMETER
ISO7220x
ISO7221x
Quiescent
TEST CONDITIONS
MIN
TYP
0.6
4.3
MAX
1
9.5
UNIT
I CC1
Supply current, V CC1
ISO7220A
ISO7221A
1 Mbps
V I = V CC or 0 V, no load
1
5
2
11
mA
ISO7221C
ISO7220x
ISO7221x
25 Mbps
Quiescent
6
8
4.3
12
18
9.5
I CC2
Supply current, V CC2
ISO7220A
ISO7221A
1 Mbps
V I = V CC or 0 V, no load
9
5
19
11
mA
ISO7221C
25 Mbps
6
12
V OH
High-level output voltage
I OH = –4 mA, See Figure 1
I OH = –20 μ A, See Figure 1
V CC – 0.4
V CC – 0.1
3
3.3
V
V OL
Low-level output voltage
I OL = 4 mA, See Figure 1
I OL = 20 μ A, See Figure 1
0.2
0
0.4
0.1
V
V I(HYS) Input voltage hysteresis
150
mV
I IH
I IL
C I
High-level input current
Low-level input current
Input capacitance to ground
IN from 0 V or V CC
IN from 0 V or V CC
IN at V CC , V I = 0.4 sin (4E6 π t)
–10
1
10
μ A
μ A
pF
CMTI
Common-mode transient immunity
V I = V CC or 0 V, See Figure 3
15
40
kV/ μ s
(1)
For the 5-V operation, V CC1 or V CC2 is specified from 4.5 V to 5.5 V.
For the 3-V operation, V CC1 or V CC2 is specified from 3 V to 3.6 V.
SWITCHING CHARACTERISTICS
V CC1 = V CC2 = 3.3 V, over recommended operating conditions (unless otherwise noted)
PARAMETER
TEST CONDITIONS
MIN
TYP
MAX
UNIT
t pLH , t pHL
PWD
Propagation delay
Pulse-width distortion |t pHL – t pLH |
(1)
ISO722xA
See Figure 1
290
400
1
485
18
ns
ns
t pLH , t pHL
PWD
Propagation delay
Pulse-width distortion |t pHL – t pLH | (1)
ISO722xC
See Figure 1
25
40
1
52
3
ns
ns
t sk(pp)
Part-to-part skew (2)
ISO722xA
ISO722xC
190
10
ns
t sk(o)
Channel-to-channel output skew
(3)
ISO722xA
ISO722xC
3
0.2
15
1
ns
t r
t f
t fs
Output signal rise time
Output signal fall time
Failsafe output delay time from input power loss
See Figure 1
See Figure 1
See Figure 2
2
2
3
ns
ns
μ s
(1)
(2)
(3)
Also referred to as pulse skew.
t sk(pp) is the magnitude of the difference in propagation delay times between any specified terminals of two devices when both devices
operate with the same supply voltages, at the same temperature, and have identical packages and test circuits.
t sk(o) is the skew between specified outputs of a single device with all driving inputs connected together and the outputs switching in the
same direction while driving identical specified loads.
Copyright ? 2009–2012, Texas Instruments Incorporated
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Product Folder Link(s): ISO7220A-Q1 ISO7221A-Q1 ISO7221C-Q1
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