参数资料
型号: ISP1563BM,557
厂商: ST-ERICSSON
元件分类: 总线控制器
英文描述: UNIVERSAL SERIAL BUS CONTROLLER, PQFP100
封装: 14 X 14 MM, 1.40 MM HEIGHT, PLASTIC, MS-026, SOT-420-1, LQFP-100
文件页数: 64/102页
文件大小: 466K
代理商: ISP1563BM,557
ISP1563_2
NXP B.V. 2007. All rights reserved.
Product data sheet
Rev. 02 — 15 March 2007
64 of 102
NXP Semiconductors
ISP1563
HS USB PCI Host Controller
11.2.3 HceOutput register
Data placed in this register by the emulation software is returned when I/O port 60h is
read and emulation is enabled. On a read of this location, OUT_FULL (bit 0 in HceStatus)
is set to logic 0. The bit allocation is given in Table 93.
[1]
The reserved bits should always be written with the reset value.
11.2.4 HceStatus register
The contents of the HceStatus register are returned on an I/O read of port 64h when
emulation is enabled. Reads from and writes to port 60h, and writes to port 64h can cause
changes in this register. Emulation software can directly access this register through its
memory address in the Host Controller’s operational register space. Accessing this
register through its memory address produces no side effects. Table 95 shows the bit
allocation.
Table 93.
HceOutput - Host Controller Emulation Output register bit allocation
Address: Content of the base address register + 108h
Bit
31
30
29
28
27
26
25
24
Symbol
reserved[1]
Reset
00000000
Access
R/W
Bit
23
22
21
20
19
18
17
16
Symbol
reserved[1]
Reset
00000000
Access
R/W
Bit
15
14
13
12
11
10
9
8
Symbol
reserved[1]
Reset
00000000
Access
R/W
Bit
7
6
5
4
3
2
1
0
Symbol
OUT_DATA[7:0]
Reset
00000000
Access
R/W
Table 94.
HceOutput - Host Controller Emulation Output register bit description
Address: Content of the base address register + 108h
Bit
Symbol
Description
31 to 8
reserved
-
7 to 0
OUT_DATA[7:0]
Output Data: This register holds the data that is returned when an I/O read of port 60h is
requested by application software.
Table 95.
HceStatus - Host Controller Emulation Status register bit allocation
Address: Content of the base address register + 10Ch
Bit
31
30
29
28
27
26
25
24
Symbol
reserved[1]
Reset
00000000
Access
R/W
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