参数资料
型号: ISP1563BM,557
厂商: ST-ERICSSON
元件分类: 总线控制器
英文描述: UNIVERSAL SERIAL BUS CONTROLLER, PQFP100
封装: 14 X 14 MM, 1.40 MM HEIGHT, PLASTIC, MS-026, SOT-420-1, LQFP-100
文件页数: 83/102页
文件大小: 466K
代理商: ISP1563BM,557
ISP1563_2
NXP B.V. 2007. All rights reserved.
Product data sheet
Rev. 02 — 15 March 2007
81 of 102
NXP Semiconductors
ISP1563
HS USB PCI Host Controller
[1]
These elds read logic 0, if the PP bit is logic 0.
2
PED
Port Enabled/Disabled: Logic 1 means enable. Logic 0 means disable. Default = 0. Ports can
only be enabled by the Host Controller as a part of the reset and enable sequence. Software
cannot enable a port by writing logic 1 to this eld. The Host Controller will only set this bit when
the reset sequence determines that the attached device is a high-speed device. Ports can be
disabled by either a fault condition or by host software. The bit status does not change until the
port state has changed. There may be a delay in disabling or enabling a port because of other
Host Controller and bus events. When the port is disabled, downstream propagation of data is
blocked on this port, except for reset.[1]
1
ECSC
Connect Status Change: Logic 1 means change in ECCS. Logic 0 means no change. Default =
0. This bit indicates a change has occurred in the ECCS of the port. The Host Controller sets this
bit for all changes to the port device connect status, even if the system software has not cleared
an existing connect status change. For example, the insertion status changes two times before
the system software has cleared the changed condition, hub hardware will be setting an
already-set bit, that is, the bit will remain set. Software clears this bit by writing logic 1 to it.[1]
0
ECCS
Current Connect Status: Logic 1 indicates a device is present on port. Logic 0 indicates no
device is present. Default = 0. This value reects the current state of the port and may not directly
correspond to the event that caused the ECSC bit to be set.[1]
Table 119. PORTSC 1, 2, 3, 4 - Port Status and Control, 1, 2, 3, 4 register bit description …continued
Address: Content of the base address register + 64h + (4
× Port Number 1) where Port Number is 1, 2, 3, 4
Bit
Symbol
Description
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