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参数资料
| 型号： | ISPLSI 1048-70LQ |
| 厂商： | Lattice Semiconductor Corporation |
| 文件页数： | 3/13页 |
| 文件大小： | 0K |
| 描述： | IC PLD ISP 96I/O 15NS 120PQFP |
| 标准包装： | 24 |
| 系列： | ispLSI® 1000 |
| 可编程类型： | 系统内可编程 |
| 最大延迟时间 tpd(1)： | 18.0ns |
| 电压电源 - 内部： | 4.75 V ~ 5.25 V |
| 逻辑元件/逻辑块数目： | 48 |
| 门数： | 8000 |
| 输入/输出数： | 96 |
| 工作温度： | 0°C ~ 70°C |
| 安装类型： | 表面贴装 |
| 封装/外壳： | 120-BQFP |
| 供应商设备封装： | 120-PQFP（28x28） |
| 包装： | 托盘 |
| 其它名称： | ISPLSI1048-70LQ |
Specifications ispLSI 1048
10
Pin Description
Input – Dedicated in-system programming enable input pin. This pin
is brought low to enable the programming mode. The MODE, SDI,
SDO and SCLK options become active.
Input – This pin performs two functions. It is a dedicated input pin when
ispEN is logic high. When ispEN is logic low, it functions as an input
pin to load programming data into the device. SDI/IN 0 also is used as
one of the two control pins for the isp state machine.
Input – This pin performs two functions. It is a dedicated input pin when
ispEN is logic high. When ispEN is logic low, it functions as a pin to
control the operation of the isp state machine.
Input/Output – This pin performs two functions. It is a dedicated input
pin when ispEN is logic high. When ispEN is logic low, it functions as
an output pin to read serial shift register data.
Input – This pin performs two functions. It is a dedicated input when
ispEN is logic high. When ispEN is logic low, it functions as a clock pin
for the Serial Shift Register.
Active Low (0) Reset pin which resets all of the GLB and I/O registers
in the device.
Dedicated Clock input. This clock input is connected to one of the
clock inputs of all of the GLBs on the device.
Dedicated clock input. This clock input is brought into the clock
distribution network, and can optionally be routed to any GLB on the
device.
Dedicated clock input. This clock input is brought into the clock
distribution network, and can optionally be routed to any GLB and/or
any I/O cell on the device.
Dedicated clock input. This clock input is brought into the clock
distribution network, and can optionally be routed to any I/O cell on the
device.
Ground (GND)
V
CC
GND
46, 76,106, 16
VCC
15, 45, 77, 107
Input/Output Pins - These are the general purpose I/O pins used by the
logic array.
I/O 0 - I/O 5
20, 21, 22, 23, 24, 25,
I/O 6 - I/O 11
26, 27, 28, 29, 30, 31,
I/O 12 - I/O 17
32, 33, 34, 35, 36, 37,
I/O 18 - I/O 23
38, 39, 40, 41, 42, 43,
I/O 24 - I/O 29
49, 50, 51, 52, 53, 54,
I/O 30 - I/O 35
55, 56, 57, 58, 59, 60,
I/O 36 - I/O 41
61, 62, 63, 64, 65, 66,
I/O 42 - I/O 47
67, 68, 69, 70, 71, 72,
I/O 48 - I/O 53
80, 81, 82, 83, 84, 85,
I/O 54 - I/O 59
86, 87, 88, 89, 90, 91,
I/O 60 - I/O 65
92, 93, 94, 95, 96, 97,
I/O 66 - I/O 71
98, 99,100,101,102,103,
I/O 72 - I/O 77
109,110,111,112,113,114,
I/O 78 - I/O 83
115,116,117,118,119,120,
I/O 84 - I/O 89
1,
2,
3,
4
5,
6,
I/O 90 - I/O 95
7,
8,
9, 10, 11, 12
IN 4
48,
IN 6 - IN 11
79,104,105, – 108, 13
Dedicated input pins to the device. (IN 2 and IN 9 not available)
RESET
18
Y0
14
Y1
78
Y2
75
Y3
74
Table 2- 0002C-48-isp
DESCRIPTION
NAME
PQFP PIN NUMBERS
ispEN
17
SDI/IN 01
19
MODE/IN 11
44
SDO/IN 31
47
SCLK/IN 51
73
1. Pins have dual function capability.
ALL
DEVICES
DISCONTINUED
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相关代理商/技术参数 |
参数描述 |
|---|---|
| ispLSI1048-70LQ | 功能描述:CPLD - 复杂可编程逻辑器件 USE ispMACH 4000V RoHS:否 制造商:Lattice 系列: 存储类型:EEPROM 大电池数量:128 最大工作频率:333 MHz 延迟时间:2.7 ns 可编程输入/输出端数量:64 工作电源电压:3.3 V 最大工作温度:+ 90 C 最小工作温度:0 C 封装 / 箱体:TQFP-100 |
| ISPLSI1048-70LT | 制造商:Lattice Semiconductor Corporation 功能描述: |
| ISPLSI1048-80LQ | 制造商:未知厂家 制造商全称:未知厂家 功能描述:Electrically-Erasable Complex PLD |
| ISPLSI1048C | 制造商:LATTICE 制造商全称:Lattice Semiconductor 功能描述:In-System Programmable High Density PLD |
| ISPLSI1048C-50LG/883 | 制造商:LATTICE 制造商全称:Lattice Semiconductor 功能描述:In-System Programmable High Density PLD |
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