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参数资料
| 型号： | ISPLSI 1048C-70LQ |
| 厂商： | Lattice Semiconductor Corporation |
| 文件页数： | 4/15页 |
| 文件大小： | 0K |
| 描述： | IC PLD ISP 96I/O 16NS 128PQFP |
| 标准包装： | 24 |
| 系列： | ispLSI® 1000 |
| 可编程类型： | 系统内可编程 |
| 最大延迟时间 tpd(1)： | 18.0ns |
| 电压电源 - 内部： | 4.75 V ~ 5.25 V |
| 逻辑元件/逻辑块数目： | 48 |
| 门数： | 8000 |
| 输入/输出数： | 96 |
| 工作温度： | 0°C ~ 70°C |
| 安装类型： | 表面贴装 |
| 封装/外壳： | 128-BQFP |
| 供应商设备封装： | 128-PQFP（28x28） |
| 包装： | 托盘 |
| 其它名称： | ISPLSI1048C-70LQ |
Specifications ispLSI 1048C
11
Pin Description
GND
B2,
B8, B13,
C8,
H3, H12,
M8,
N2,
N8
VCC
C7,
G2,
G3, G12, G13,
M7,
N7
I/O 0 - I/O 5
J2,
J3,
K1,
L1,
K2,
M1,
I/O 6 - I/O 11
L2,
K3,
N1,
M2,
L3,
P1,
I/O 12 - I/O 17
M3,
P2,
N3,
M4,
P3,
N4,
I/O 18 - I/O 23
P4,
M5,
N5,
P5,
M6,
N6,
I/O 24 - I/O 29
N9,
M9, P10, P11, N10, P12,
I/O 30 - I/O 35
N11, M10, P13, N12, M11, P14,
I/O 36 - I/O 41
M12, N14, M13, L12, M14, L13,
I/O 42 - I/O 47
L14, K12, K13, K14, J12, J13,
I/O 48 - I/O 53
F13, F12, E14, D14, E13, C14,
I/O 54 - I/O 59
D13, E12, B14, C13, D12, A14,
I/O 60 - I/O 65
C12, A13, B12, C11, A12, B11,
I/O 66 - I/O 71
A11, C10, B10, A10,
C9,
B9,
I/O 72 - I/O 77
B6,
C6,
A5,
A4,
B5,
A3,
I/O 78 - I/O 83
B4,
C5,
A2,
B3,
C4,
A1,
I/O 84 - I/O 89
C3,
B1,
C2,
D3,
C1,
D2,
I/O 90 - I/O 95
D1,
E3,
E2,
E1,
F3,
F2
RESET
H1
Y0
G1
Y1
G14
Y2
H13
Y3
H14
IN 2, IN 4
P7,
P9
IN 6 - IN 11
F14,
A9,
A8,
A7,
A6,
F1
GOE0, GOE1
N13,
B7,
Input – Dedicated in-system programming enable input pin. This
pin is brought low to enable the programming mode. The MODE,
SDI, SDO and SCLK options become active.
Input – This pin performs two functions. It is a dedicated input pin
when ispEN is logic high. When ispEN is logic low, it functions as
an input pin to load programming data into the device. SDI/IN 0
also is used as one of the two control pins for the isp state machine.
Input – This pin performs two functions. It is a dedicated input pin
when ispEN is logic high. When ispEN is logic low, it functions as
a pin to control the operation of the isp state machine.
Input/Output – This pin performs two functions. It is a dedicated
input pin when ispEN is logic high. When ispEN is logic low, it
functions as an output pin to read serial shift register data.
Input – This pin performs two functions. It is a dedicated input
when ispEN is logic high. When ispEN is logic low, it functions as
a clock pin for the Serial Shift Register.
Input/Output Pins - These are the general purpose I/O pins used
by the logic array.
Ground (GND)
V
CC
Active Low (0) Reset pin which resets all of the GLB and I/O
registers in the device.
Dedicated Clock input. This clock input is connected to one of the
clock inputs of all of the GLBs on the device.
Dedicated clock input. This clock input is brought into the clock
distribution network, and can optionally be routed to any GLB on
the device.
Dedicated clock input. This clock input is brought into the clock
distribution network, and can optionally be routed to any GLB and/
or any I/O cell on the device.
Dedicated clock input. This clock input is brought into the clock
distribution network, and can optionally be routed to any I/O cell on
the device.
Dedicated input pins to the device.
Global output enables for all I/Os.
Table 2- 0002C-48C/CPGA
DESCRIPTION
NAME
CPGA PIN NUMBERS
ispEN
H2
SDI/IN 01
J1
MODE/IN 11
P6
SDO/IN 31
P8
SCLK/IN 51
J14
1. Pins have dual function capability.
ALL
DEVICES
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相关代理商/技术参数 |
参数描述 |
|---|---|
| ispLSI1048C-70LQ | 功能描述:CPLD - 复杂可编程逻辑器件 USE ispMACH 4000V RoHS:否 制造商:Lattice 系列: 存储类型:EEPROM 大电池数量:128 最大工作频率:333 MHz 延迟时间:2.7 ns 可编程输入/输出端数量:64 工作电源电压:3.3 V 最大工作温度:+ 90 C 最小工作温度:0 C 封装 / 箱体:TQFP-100 |
| ISPLSI1048E | 制造商:LATTICE 制造商全称:Lattice Semiconductor 功能描述:In-System Programmable High Density PLD |
| ISPLSI1048E_06 | 制造商:LATTICE 制造商全称:Lattice Semiconductor 功能描述:In-System Programmable High Density PLD |
| ISPLSI1048E100LQ | 制造商:LATTICE 制造商全称:Lattice Semiconductor 功能描述:In-System Programmable High Density PLD |
| ISPLSI1048E-100LQ | 制造商:未知厂家 制造商全称:未知厂家 功能描述:Electrically-Erasable Complex PLD |
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