
14
XMEGA A [MANUAL]
8077I–AVR–11/2012
3.14
Register Descriptions
3.14.1 CCP – Configuration Change Protection register
Bit 7:0 – CCP[7:0]: Configuration Change Protection
The CCP register must be written with the correct signature to enable change of the protected I/O register or execution of
the protected instruction for a maximum period of four CPU instruction cycles. All interrupts are ignored during these
cycles. After these cycles, interrupts will automatically be handled again by the CPU, and any pending interrupts will be
executed according to their level and priority. When the protected I/O register signature is written, CCP[0] will read as
one as long as the protected feature is enabled. Similarly when the protected SPM/LPM signature is written, CCP[1] will
read as one as long as the protected feature is enabled. CCP[7:2] will always read as zero.
Table 3-1 on page 14 shows
the signature for the various modes.
Table 3-1.
Modes of CPU change protection.
3.14.2 RAMPD – Extended Direct Addressing register
This register is concatenated with the operand for direct addressing (LDS/STS) of the whole data memory space on
devices with more than 64KB of data memory. This register is not available if the data memory, including external
memory, is less than 64KB.
Bit 7:0 – RAMPD[7:0]: Extended Direct Addressing bits
These bits hold the MSB of the 24-bit address created by RAMPD and the 16-bit operand. Only the number of bits
required to address the available data memory is implemented for each device. Unused bits will always read as zero.
Bit
76543210
+0x04
CCP[7:0]
Read/Write
WWWWWW
R/W
Initial Value
00000000
Signature
Group Configuration
Description
0x9D
SPM
Protected SPM/LPM
0xD8
IOREG
Protected IO register
Bit
765
4321
0
+0x08
RAMPD[7:0]
Read/Write
R/W
Initial Value
000
0000
0