参数资料
型号: IXDE504D2T/R
厂商: IXYS
文件页数: 11/13页
文件大小: 0K
描述: IC GATE DRIVER 4A 8-DFN
标准包装: 2,500
配置: 低端
输入类型: 反相
延迟时间: 19ns
电流 - 峰: 4A
配置数: 2
输出数: 2
电源电压: 4.5 V ~ 30 V
工作温度: -55°C ~ 125°C
安装类型: 表面贴装
封装/外壳: 8-VFDFN
供应商设备封装: 8-DFN(5x4)
包装: 带卷 (TR)
IXDD504 / IXDE504
APPLICATIONS INFORMATION
Short Circuit di/dt Limit
A short circuit in a high-power MOSFET such as the IXFN100N20,
(20A, 1000V), as shown in Figure 32, can cause the current
through the module to flow in excess of 60A for 10 μ s or more
prior to self-destruction due to thermal runaway. For this
reason, some protection circuitry is needed to turn off the
MOSFET module. However, if the module is switched off too
fast, there is a danger of voltage transients occuring on the
drain due to Ldi/dt, (where L represents total inductance in
series with drain). If these voltage transients exceed the
MOSFET's voltage rating, this can cause an avalanche break-
down.
The IXDD504 and IXDE504 have the unique capability, with
additional circuitry, to softly switch off the high-power MOSFET
module, significantly reducing these Ldi/dt transients.
Thus, the IXDD504 & IXDE504 help to prevent device destruc-
tion from both dangers; over-current, and avalanche break-
down due to di/dt induced over-voltage transients.
The IXDD504 & IXDE504 are designed to not only provide ± 4A
per output under normal conditions, but also to allow their
outputs to go into a high impedance state. This permits the
IXDD504 or IXDE504 outputs to control a separate weak pull-
down circuit during detected overcurrent shutdown conditions
to limit and separately control d VGS /dt gate turnoff. This circuit
is shown in Figure 33.
Referring to Figure 33, the protection circuitry should include
a comparator, whose positive input is connected to the source
of the IXFN100N20. A low pass filter should be added to the
input of the comparator to eliminate any glitches in voltage
caused by the inductance of the wire connecting the source
resistor to ground. (Those glitches might cause false triggering
of the comparator).
The comparator's output should be connected to a SRFF(Set
Reset Flip Flop). The flip-flop controls both the Enable signal,
and the low power MOSFET gate. Please note that CMOS 4000-
series devices operate with a V CC range from 3 to 15 VDC, (with
18 VDC being the maximum allowable limit).
A low power MOSFET, such as the 2N7002, in series with a
resistor, will enable the IXFN100N20 gate voltage to drop
gradually. The resistor should be chosen so that the RC time
constant will be 100us, where "C" is the Miller capacitance of
the IXFN100N20.
For resuming normal operation, a Reset signal is needed at
the SRFF's input to enable the IXDD504 again. This Reset can
be generated by connecting a One Shot circuit between the
IXDD504 Input signal and the SRFF restart input. The One Shot
will create a pulse on the rise of the IXDD504 input, and this
pulse will reset the SRFF outputs to normal operation.
When a short circuit occurs, the voltage drop across the low-
value, current-sensing resistor, (Rs=0.005 Ohm), connected
between the MOSFET Source and ground, increases. This
triggers the comparator at a preset level. The SRFF drives a low
input into the Enable pin disabling the IXDD504 output. The
SRFF also turns on the low power MOSFET, (2N7000).
In this way, the high-power MOSFET module is softly turned off
by the IXDD504, preventing its destruction.
Figure 33 - Application Test Diagram
IXDD504
Ld
10uH
Rd
0.1
+
-
VB
+
-
VCC
+
-
VIN
VCC
IN
EN
DGND
OUT
Rsh
1600
Rg
1
IXFN100N20
Low_Power
2N7000
R+
10k
Rs
Ls
20nH
One Shot Circuit
Rcomp
Comp
NOT1
CD4049A
Ros
1M
Cos
1pF
NAND
CD4011A
NOT2
CD4049A
Q
R
5k
Ccomp
1pF
LM339
V+
V-
+
-
REF
+
-
C+
100pF
NOT3
CD4049A
NOR1
CD4001A
S
EN
NOR2
CD4001A
SR Flip-Flop
11
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