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参数资料
| 型号： | IXF1010 |
| 厂商： | INTEL CORP |
| 元件分类： | 微控制器/微处理器 |
| 英文描述： | 10 CHANNEL(S), 1000M bps, LOCAL AREA NETWORK CONTROLLER, CBGA552 |
| 封装： | 25 X 25 MM, 1 MM PITCH, CERAMIC, BGA-552 |
| 文件页数： | 35/116页 |
| 文件大小： | 1392K |
| 代理商： | IXF1010 |
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10-Port 100/1000 Mbps Ethernet MAC — IXF1010
Preliminary Datasheet
25
Document #: 249839
Revision #: 001
Rev. Date: April 29, 2002
3.2
System Packet Interface Level 4 Phase 2
The System Packet Interface Level 4 Phase 2 (SPI4-2) provides a high-speed connection to a
network processor or an ASIC. The interface implemented on the IXF1010 operates at data rates up
to 12.8 Gbps and supports up to ten 1 Gbps MAC channels in the IXF1010. The data path is 16
lanes wide in each direction, with each lane operating at up to 800 Mbps. Port addressing, start/end
packet control, and error control codes are all transferred “In-band” on the data bus. In-band
addressing supports up to 10 ports. Separate transmit and receive FIFO status lines are used for
flow control. By keeping the FIFO status information out-of-band, the transmit and receive
interfaces may be decoupled to operate independently.
3.2.1
Data Path
Transfer of complete packets or shorter bursts is controlled by the programmed MaxBurst1 or
MaxBurst2 in conjunction with the FIFO status bus. The maximum configured payload data
transfer size must be a multiple of 16 bytes. Control words are inserted between burst transfers
only. Once a transfer begins, data words are sent uninterrupted until end-of-packet, or until a
multiple of 16 bytes is reached as programmed in MaxBurst1 and MaxBurst2. The interval
between the end of a given transfer and the next payload control word (marking the start of another
transfer) consists of zero or more idle control words and/or training patterns.
Note:
The system designer should be aware that the MAC Transfer Threshold Register must be set to a
value which exceeds MaxBurst1 number of bytes. Otherwise, a TX FIFO under-run may result.
The minimum and maximum supported packet lengths are determined by the application. Because
the IXF1010 is targeted at the Ethernet Environment, the minimum frame size is 64 bytes and the
maximum frame size is 1522 bytes for VLAN packets (1518 bytes for non-VLAN packets). For
larger frames, adjust the Max Frame Size Register value, seen in Table 50 on page 78. However,
for ease of implementation, successive start-of-packets must occur not less than eight cycles apart,
where a cycle is one control or data word. The gap between shorter packets is filled with idle
control words.
Note:
Data Packets with frame lengths less than 64 bytes cannot be transferred to the IXF1010 unless
packet padding is enabled. If this rule is disregarded, unwanted fragments may be generated on the
network at the RGMII interface.
Figure 6 on page 26 shows cycle-by-cycle behavior of the data path for valid state transitions. The
states correspond to the type of words transferred on the data path. Transitions from the “Data
Burst” state (to “Payload Control” or “Idle Control”) are possible only on the integer multiples of
eight cycles (corresponding to multiples of 16-byte segmentations) or upon end-of-packet. A data
burst must immediately follow a payload control word on the next cycle. Arcs not annotated
correspond to single cycles.
In the IXF1010, the RX FIFO Status channel operates in a pessimistic mode. For example, if there
is a DIP-2 check error found, all previously granted credits are cancelled and the internal status for
each channel is set to SATISFIED. Any current data burst in transmission is completed. No new
credits are granted until a complete FIFO status cycle has been received and validated by a correct
DIP-2 check. This is the only method of operation that can eliminate the possibility of an overrun
in the link partner device. It is termed as pessimistic because it has the longest latency and largest
impact on usable bandwidth. However, as a DIP-2 check error is a rare event, there will be no ‘real
world’ effect on bandwidth utilization and no possibility of data loss.
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