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参数资料
型号： IXF1010
厂商： INTEL CORP
元件分类： 微控制器/微处理器
英文描述： 10 CHANNEL(S), 1000M bps, LOCAL AREA NETWORK CONTROLLER, CBGA552
封装： 25 X 25 MM, 1 MM PITCH, CERAMIC, BGA-552
文件页数： 45/116页
文件大小： 1392K
代理商： IXF1010
IXF1010 — 10-Port 100/1000 Mbps Ethernet MAC
34
Preliminary Datasheet
Document #: 249839
Revision #: 001
Rev. Date: April 29, 2002
3.3
Reduced Gigabit Media Independent Interface (RGMII)
IXF1010 supports Reduced Gigabit Media Independent Interface (RGMII) standards as defined in
the Hewlett-Packard RGMII Version 1.2a specification. The RGMII is an alternative to the IEEE
802.3u MII, the IEEE 802.3z GMII, and the Ten-Bit Interface (TBI).
3.3.1
Purpose
The RGMII reduces the number of pins required to interconnect the MAC and the PHY, from a
maximum of 28 pins (TBI) to 12 pins, in a cost-effective and technology-independent manner. The
data paths and all associated control signals are reduced, control signals are multiplexed together,
and both edges of the clock are used. For Gigabit operation, the clocks operate at 125 MHz, and for
100 Mbps operation, the clocks operate at 25 MHz. For 100 Mbps operation, the RGMII interface
data path reverts to standard MII operational mode, as defined in IEEE 802.3, Clause 22. The
multiplexed control signals operate as defined in RGMII Specification 1.2a.
3.3.2
1000 Mbps Operation
3.3.2.1
Multiplexing of Data and Control
Multiplexing of data and control information is achieved by utilizing both edges of the reference
clocks and sending the lower 4 bits on the rising edge and the upper 4 bits on the falling edge.
Control signals are multiplexed into a single clock cycle using the same technique (see Figure 19,
“RGMII 1000 Mbps Multiplexing and Timing Diagram” on page 55).
3.3.2.2
Timing Specifics
This interface requires that the clock and data are generated simultaneously by the source of the
signals, thus skew between the clock and data is critical for proper operation. This approach is used
to provide tighter control of skew. Table 20, “RGMII 1000 Mbps Timing Specifics” on page 55
provides these timing specifics.
3.3.3
100 Mbps Operation
3.3.3.1
Multiplexing of Data and Control
The control signals are multiplexed, as in the 1000 Mbps operation, by using both edges of the
clock. The data signals, however, do not need to be multiplexed. The data signals are driven off the
rising edge of the clock. The clock rate is reduced to 25 MHz for 100 Mbps operation. The MAC
generates the Transmit Reference Clock (TXC) and the Receive Reference Clock (RXC) is
generated by the PHY. During packet reception, the RXC is stretched on either the positive or
negative pulse to accommodate transition from the free-running clock to a data-synchronous clock
domain (see Figure 20, “RGMII 100 Mbps Multiplexing and Timing Diagram” on page 57.
3.3.3.2
Timing Specifics
Skew between the clock and data is critical to proper operation, so timing for this interface allows
simultaneous generation of the clock and data by the source. This approach is used to provide
tighter control of skew. Table 22, “RGMII 100 Mbps Timing Specifics” on page 57 provides these
timing specifics.
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