参数资料
型号: KAC-9627
厂商: Eastman Kodak Company
文件页数: 21/41页
文件大小: 0K
描述: IC SENSOR IMAGE VGA 48CLCC
标准包装: 480
象素大小: 7.5µm x 7.5µm
有源象素阵列: 648H x 488V
每秒帧数: 30
电源电压: 3.3V
类型: CMOS 成像
封装/外壳: 48-LCC
供应商设备封装: 48-LCC(14.22x14.22)
包装: 散装
请注意: *
其它名称: LM9627
IMAGE SENSOR SOLUTIONS
Functional Description (continued)
10.0 SERIAL BUS
The serial bus interface consists of the sda (serial data), sclk
(serial clock) and sadr (device address select) pins. The KAC-
9627 can operate only as a slave.
The sclk pin is an input, it only and controls the serial interface,
all other clock functions within KAC-9627 use the master clock
10.4 Data Valid
The master must ensure that data is stable during the logic 1
state of the sclk pin. All transitions on the sda pin can only occur
when the logic level on the sclk pin is “0” as shown in Figure 33.
sda
pin, mclk .
sclk
10.1 Start/Stop Conditions
The serial bus will recognize a logic 1 to logic 0 transition on the
sda pin while the sclk pin is at logic 1 as the start condition. A
data line
stable;
data valid
change
of data
allowed
data line
stable;
data valid
logic 0 to logic 1 transition on the sda pin while the sclk pin is at
logic 1 is interrupted as the stop condition as shown in Figure
31.
sda
sclk
Figure 33. Data Validity
10.5 Byte Format
Every byte consists of 8 bits. Each byte transferred on the bus
must be followed by an Acknowledge . The most significant bit of
the byte is should always be transmitted first. See Figure 34.
S
start condition
P
stop condition
10.6 Write Operation
A write operation is initiated by the master with a Start Condition
followed by the sensor ’s Device Address and Write bit. When
Figure 31. Start/Stop Conditions
10.2 Device Address
The serial bus Device Address of the KAC-9627 is set to
1010101 when sadr is tied low and 0110011 when sadr is tied
high. The value for s adr is set at power up.
10.3 Acknowledgment
The KAC-9627 will hold the value of the sda pin to a logic 0 dur-
ing the logic 1 state of the Acknowledge clock pulse on sclk as
shown in Figure 32.
the master receives an Acknowledge from the sensor it can
transmit 8 bit internal register address. The sensor will respond
with a second Acknowledge signaling the master to transmit 8
write data bits. A third Acknowledge is issued by the sensor
when the data has been successfully received.
The write operation is completed when the master asserts a
Stop Condition or a second Start Condition . See Figure 35.
10.7 Read Operation
A read operation is initiated by the master with a Start Condition
followed by the sensor ’s Device Address and Write bit. When
the master receives an Acknowledge from the sensor it can
sda
from master
sda
from sensor
MSB
ACK
ACK
transmit the internal Register Address byte. The sensor will
respond with a second Acknowledge . The master must then
issue a new Start Condition followed by the sensor ’s Device
Address and read bit. The sensor will respond with an Acknowl-
sclk
S
START
1 2 7
Figure 32. Acknowledge
8
9
Clock pulse
for ACK
edged followed by the Read Data byte.
The read operation is completed when the master asserts a Not
Acknowledge followed by Stop Condition or a second Start Con-
dition . See Figure 36.
sda
MSB
ack signal
from receiver
ack signal
from receiver
byte complete
sclk
1
2
7
8
9
ACK clock line
1
2
8
9
ACK
S
held low
Figure 34. Serial Bus Byte Format
P
S
Device
Address
W
A
Register
Address
A
Data
Byte
A
P
bold sensor action
Figure 35. Serial Bus Write Operation
S
Device
Address
W
A
Register
Address
A
S
Device
Address
R
A
Data
Byte
_
A
P
bold sensor action
Figure 36. Serial Bus Read Operation
www.kodak.com/go/imagers 585-722-4385
21
Email:imagers@kodak.com
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