参数资料
| 型号： | KAD5514P-12Q72 |
| 厂商： | Intersil |
| 文件页数： | 13/34页 |
| 文件大小： | 0K |
| 描述： | IC ADC 14BIT 125MSPS SGL 72-QFN |
| 产品培训模块： | High-Speed Analog-to-Digital Converters |
| 标准包装： | 1 |
| 系列： | FemtoCharge™ |
| 位数： | 14 |
| 采样率（每秒）： | 125M |
| 数据接口： | 串行，SPI? |
| 转换器数目： | 1 |
| 功率耗散（最大）： | 376mW |
| 电压电源： | 单电源 |
| 工作温度： | -40°C ~ 85°C |
| 安装类型： | 表面贴装 |
| 封装/外壳： | 72-VFQFN 裸露焊盘 |
| 供应商设备封装： | 72-QFN（10x10） |
| 包装： | 托盘 |
| 输入数目和类型： | 1 个差分，单极 |
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20
FN6804.2
September 10, 2009
The clock divider can also be controlled through the SPI
port, which overrides the CLKDIV pin setting. Details on this
are contained in “Serial Peripheral Interface” on page 22.
A delay-locked loop (DLL) generates internal clock signals
for various stages within the charge pipeline. If the frequency
of the input clock changes, the DLL may take up to 52s to
regain lock at 250MSPS. The lock time is inversely
proportional to the sample rate.
The DLL has two ranges of operation, slow and fast. The
slow range can be used for sample rates between 40MSPS
and 100MSPS, while the default fast range can be used from
80MSPS to the maximum specified sample rate.
Jitter
In a sampled data system, clock jitter directly impacts the
achievable SNR performance. The theoretical relationship
is illustrated in Figure 32.
This relationship shows the SNR that would be achieved if
clock jitter were the only non-ideal factor. In reality,
achievable SNR is limited by internal factors such as
linearity, aperture jitter and thermal noise. Internal aperture
jitter is the uncertainty in the sampling instant shown in
Figure 1. The internal aperture jitter combines with the input
clock jitter in a root-sum-square fashion, since they are not
statistically correlated, and this determines the total jitter in
the system. The total jitter, combined with other noise
sources, then determines the achievable SNR.
Voltage Reference
A temperature compensated voltage reference provides the
reference charges used in the successive approximation
operations. The full-scale range of each A/D is proportional
to the reference voltage. The voltage reference is internally
bypassed and is not accessible to the user.
Digital Outputs
Output data is available as a parallel bus in
LVDS-compatible or CMOS modes. Additionally, the data
can be presented in either double data rate (DDR) or single
data rate (SDR) formats. The even numbered data output
pins are active in DDR mode in the 72 pin package option.
When CLKOUT is low the MSB and all odd logical bits are
output, while on the high phase the LSB and all even logical
bits are presented (this is true in both the 72 pin and 48 pin
timing relationships for LVDS/CMOS and DDR/SDR modes.
The 48 Ld QFN package option contains seven LVDS data
output pin pairs, and therefore can only support DDR mode.
Additionally, the drive current for LVDS mode can be set to a
nominal 3mA or a power-saving 2mA. The lower current
setting can be used in designs where the receiver is in close
physical proximity to the ADC. The applicability of this setting
is dependent upon the PCB layout, therefore the user should
experiment to determine if performance degradation is
observed.
The output mode and LVDS drive current are selected via
the OUTMODE pin as shown in Table 2.
The output mode can also be controlled through the SPI
port, which overrides the OUTMODE pin setting. Details on
this are contained in the “Serial Peripheral Interface” on
An external resistor creates the bias for the LVDS drivers. A
10k
Ω, 1% resistor must be connected from the RLVDS pin to
OVSS.
Over-Range Indicator
The over-range (OR) bit is asserted when the output code
reaches positive full-scale (e.g. 0xFFF in offset binary mode).
The output code does not wrap around during an over-range
condition. The OR bit is updated at the sample rate.
Power Dissipation
The power dissipated by the KAD5514P is primarily
dependent on the sample rate and the output modes: LVDS
vs CMOS and DDR vs SDR. There is a static bias in the
analog supply, while the remaining power dissipation is
linearly related to the sample rate. The output supply
dissipation changes to a lesser degree in LVDS mode, but is
more strongly related to the clock frequency in CMOS mode.
TABLE 1. CLKDIV PIN SETTINGS
CLKDIV PIN
DIVIDE RATIO
AVSS
2
Float
1
AVDD
4
SNR
20 log
10
1
2
πf
IN tJ
--------------------
=
(EQ. 1)
FIGURE 32. SNR vs CLOCK JITTER
tj = 100ps
tj = 10ps
tj = 1ps
tj = 0.1ps
10 BITS
12 BITS
14 BITS
50
55
60
65
70
75
80
85
90
95
100
1M
10M
100M
1G
SNR
(dB)
INPUT FREQUENCY (Hz)
TABLE 2. OUTMODE PIN SETTINGS
OUTMODE PIN
MODE
AVSS
LVCMOS
Float
LVDS, 3mA
AVDD
LVDS, 2mA
KAD5514P
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相关代理商/技术参数 |
参数描述 |
|---|---|
| KAD5514P-17Q48 | 制造商:INTERSIL 制造商全称:Intersil Corporation 功能描述:14-Bit, 250/210/170/125MSPS ADC |
| KAD5514P-17Q72 | 制造商:Intersil Corporation 功能描述:14-BIT, 170MSPS SINGLE-CHANNEL ADC, PROGRAMMABLE LVDS/LVCMOS - Rail/Tube 制造商:Intersil Corporation 功能描述:IC ADC 14BIT 170MSPS SGL 72-QFN |
| KAD5514P-21Q48 | 制造商:Intersil Corporation 功能描述:14-BIT, 210MSPS SINGLE-CHANNEL ADC, PROGRAMMABLE LVDS/LVCMOS - Rail/Tube 制造商:Intersil Corporation 功能描述:IC ADC 14BIT 210MSPS SGL 48-QFN |
| KAD5514P-21Q72 | 制造商:Intersil Corporation 功能描述:14-BIT, 210MSPS SINGLE-CHANNEL ADC, PROGRAMMABLE LVDS/LVCMOS - Rail/Tube 制造商:Intersil Corporation 功能描述:IC ADC 14BIT 210MSPS SGL 72-QFN |
| KAD5514P-25Q48 | 制造商:Intersil Corporation 功能描述:14-BIT, 250MSPS SINGLE-CHANNEL ADC, PROGRAMMABLE LVDS/LVCMOS - Rail/Tube 制造商:Intersil Corporation 功能描述:IC ADC 14BIT 250MSPS SGL 48-QFN 制造商:Intersil Corporation 功能描述:IC, ADC, 14BIT, Resolution (Bits):14bit, Sampling Rate:250MSPS, Supply Voltage T 制造商:Intersil Corporation 功能描述:IC, ADC, 14BIT, Resolution (Bits):14bit, Sampling Rate:250MSPS, Supply Voltage Type:Single, Supply Voltage Min:1.7V, Supply Voltage Max:1.9V, Supply Current:170mA, Digital IC Case Style:QFN, No. of Pins:48, Data Interface:SPI, MSL:- , RoHS Compliant: Yes |
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