参数资料
型号: KAD5514P-12Q72
厂商: Intersil
文件页数: 15/34页
文件大小: 0K
描述: IC ADC 14BIT 125MSPS SGL 72-QFN
产品培训模块: High-Speed Analog-to-Digital Converters
标准包装: 1
系列: FemtoCharge™
位数: 14
采样率(每秒): 125M
数据接口: 串行,SPI?
转换器数目: 1
功率耗散(最大): 376mW
电压电源: 单电源
工作温度: -40°C ~ 85°C
安装类型: 表面贴装
封装/外壳: 72-VFQFN 裸露焊盘
供应商设备封装: 72-QFN(10x10)
包装: 托盘
输入数目和类型: 1 个差分,单极
22
FN6804.2
September 10, 2009
Mapping of the input voltage to the various data formats is
shown in Table 5.
Serial Peripheral Interface
A serial peripheral interface (SPI) bus is used to facilitate
configuration of the device and to optimize performance. The
SPI bus consists of chip select (CSB), serial clock (SCLK)
serial data input (SDI), and serial data input/output (SDIO).
The maximum SCLK rate is equal to the ADC sample rate
(fSAMPLE) divided by 16 for write operations and fSAMPLE
divided by 66 for reads. At fSAMPLE = 250MHz, maximum
SCLK is 15.63MHz for writing and 3.79MHz for read
operations. There is no minimum SCLK rate.
The following sections describe various registers that are
used to configure the SPI or adjust performance or functional
parameters. Many registers in the available address space
(0x00 to 0xFF) are not defined in this document. Additionally,
within a defined register there may be certain bits or bit
combinations that are reserved. Undefined registers and
undefined values within defined registers are reserved and
should not be selected. Setting any reserved register or value
may produce indeterminate results.
FIGURE 34. GRAY CODE TO BINARY CONVERSION
12
13
11
0
1
BINARY
12
13
11
0
GRAY CODE
1
TABLE 5. INPUT VOLTAGE TO OUTPUT CODE MAPPING
INPUT
VOLTAGE
OFFSET BINARY
TWO’S
COMPLEMENT
GRAY CODE
–Full Scale
000 00 000 00 00 00
100 00 000 00 00 00
000 00 000 00 00 00
–Full Scale
+ 1LSB
000 00 000 00 00 01
100 00 000 00 00 01
000 00 000 00 00 01
Mid–Scale
100 00 000 00 00 00
000 00 000 00 00 00
110 00 000 00 00 00
+Full Scale
– 1LSB
111 11 111 11 11 10
011 11 111 11 11 10
100 00 000 00 00 01
+Full Scale
111 11 111 11 11 11
011 11 111 111 11 1
100 00 000 00 00 00
FIGURE 35. MSB-FIRST ADDRESSING
CSB
SCLK
SDIO
R/W
W1
W0
A12
A11
A1
A0
D7
D6
D5
D4
D3
D2
D1D
0
A10
FIGURE 36. LSB-FIRST ADDRESSING
CSB
SCLK
SDIO
R/W
W1
W0
A12
A11
A1
A0
D7
D6
D5
D4
D3
D2
D1
D0
A2
KAD5514P
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