参数资料
| 型号： | KAD5610P-25Q72 |
| 厂商： | Intersil |
| 文件页数： | 8/30页 |
| 文件大小： | 0K |
| 描述： | IC ADC 10BIT 250MSPS DUAL 72-QFN |
| 产品培训模块： | High-Speed Analog-to-Digital Converters |
| 标准包装： | 1 |
| 系列： | FemtoCharge™ |
| 位数： | 10 |
| 采样率（每秒）： | 250M |
| 数据接口： | 串行，SPI? |
| 转换器数目： | 2 |
| 功率耗散（最大）： | 438mW |
| 电压电源： | 单电源 |
| 工作温度： | -40°C ~ 85°C |
| 安装类型： | 表面贴装 |
| 封装/外壳： | 72-VFQFN 裸露焊盘 |
| 供应商设备封装： | 72-QFN（10x10） |
| 包装： | 托盘 |
| 输入数目和类型： | 2 个差分，单极 |
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16
FN6810.2
September 10, 2009
An RF transformer will give the best noise and distortion
performance for wideband and/or high intermediate
frequency (IF) inputs. Two different transformer input
This dual transformer scheme is used to improve common-
mode rejection, which keeps the common-mode level of the
input matched to VCM. The value of the shunt resistor
should be determined based on the desired load impedance.
The differential input resistance of the KAD5610P is 1000
Ω.
The SHA design uses a switched capacitor input stage
(see Figure 42), which creates current spikes when the
sampling capacitance is reconnected to the input voltage.
This causes a disturbance at the input which must settle
before the next sampling point. Lower source impedance will
result in faster settling and improved performance. Therefore
a 1:1 transformer and low shunt resistance are
recommended for optimal performance.
A differential amplifier, as shown in Figure 29, can be used in
applications that require DC-coupling. In this configuration
the amplifier will typically dominate the achievable SNR and
distortion performance.
Clock Input
The clock input circuit is a differential pair (see Figure 43).
Driving these inputs with a high level (up to 1.8VP-P on each
input) sine or square wave will provide the lowest jitter
performance. A transformer with 4:1 impedance ratio will
provide increased drive levels.
The recommended drive circuit is shown in Figure 30. A duty
range of 40% to 60% is acceptable. The clock can be driven
single-ended, but this will reduce the edge rate and may
impact SNR performance. The clock inputs are internally
self-biased to AVDD/2 to facilitate AC coupling.
A selectable 2x frequency divider is provided in series with
the clock input. The divider can be used in the 2x mode with
a sample clock equal to twice the desired sample rate. This
allows the use of the Phase Slip feature, which enables
synchronization of multiple ADCs.
The clock divider can also be controlled through the SPI
port, which overrides the CLKDIV pin setting. Details on this
are contained in “Serial Peripheral Interface” on page 21.
A delay-locked loop (DLL) generates internal clock signals
for various stages within the charge pipeline. If the frequency
of the input clock changes, the DLL may take up to 52ìs to
regain lock at 250MSPS. The lock time is inversely
proportional to the sample rate.
Jitter
In a sampled data system, clock jitter directly impacts the
achievable SNR performance. The theoretical relationship
is illustrated in Figure 31.
FIGURE 27. TRANSFORMER INPUT FOR GENERAL
PURPOSE APPLICATIONS
ADT1-1WT
0.1F
KAD5610P
VCM
ADT1-1WT
1000pF
FIGURE 28. TRANSMISSION-LINE TRANSFORMER INPUT
FOR HIGH IF APPLICATIONS
ADTL1-12
0.1F
KAD5610P
VCM
ADTL1-12
1000pF
FIGURE 29. DIFFERENTIAL AMPLIFIER INPUT
KAD5610P
VCM
0.1F
0.22F
69.8O
49.9O
100O
69.8O
348O
CM
217O
25O
Ω
TABLE 1. CLKDIV PIN SETTINGS
CLKDIV PIN
DIVIDE RATIO
AVSS
2
Float
1
AVDD
4
FIGURE 30. RECOMMENDED CLOCK DRIVE
TC4-1W
200pF
200O
200pF
CLKP
CLKN
1000pF
Ω
SNR
20 log
10
1
2
πf
IN tJ
--------------------
=
(EQ. 1)
KAD5610P
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相关代理商/技术参数 |
参数描述 |
|---|---|
| KAD5612P | 制造商:INTERSIL 制造商全称:Intersil Corporation 功能描述:Dual 12-Bit, 250/210/170/125MSPS A/D Converter |
| KAD5612P_09 | 制造商:INTERSIL 制造商全称:Intersil Corporation 功能描述:Dual 12-Bit, 250/210/170/125MSPS A/D Converter |
| KAD5612P_0909 | 制造商:INTERSIL 制造商全称:Intersil Corporation 功能描述:Dual 12-Bit, 250/210/170/125MSPS A/D Converter |
| KAD5612P-12Q72 | 功能描述:IC ADC 12BIT 125MSPS DUAL 72-QFN RoHS:是 类别:集成电路 (IC) >> 数据采集 - 模数转换器 系列:FemtoCharge™ 产品培训模块:Lead (SnPb) Finish for COTS Obsolescence Mitigation Program 标准包装:250 系列:- 位数:12 采样率（每秒）:1.8M 数据接口:并联 转换器数目:1 功率耗散（最大）:1.82W 电压电源:模拟和数字 工作温度:-40°C ~ 85°C 安装类型:表面贴装 封装/外壳:48-LQFP 供应商设备封装:48-LQFP（7x7） 包装:管件 输入数目和类型:2 个单端，单极 |
| KAD5612P-17Q72 | 功能描述:IC ADC 12BIT 170MSPS DUAL 72-QFN RoHS:是 类别:集成电路 (IC) >> 数据采集 - 模数转换器 系列:FemtoCharge™ 产品培训模块:Lead (SnPb) Finish for COTS Obsolescence Mitigation Program 标准包装:250 系列:- 位数:12 采样率（每秒）:1.8M 数据接口:并联 转换器数目:1 功率耗散（最大）:1.82W 电压电源:模拟和数字 工作温度:-40°C ~ 85°C 安装类型:表面贴装 封装/外壳:48-LQFP 供应商设备封装:48-LQFP（7x7） 包装:管件 输入数目和类型:2 个单端，单极 |
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