参数资料
| 型号： | KAD5610P-25Q72 |
| 厂商： | Intersil |
| 文件页数： | 9/30页 |
| 文件大小： | 0K |
| 描述： | IC ADC 10BIT 250MSPS DUAL 72-QFN |
| 产品培训模块： | High-Speed Analog-to-Digital Converters |
| 标准包装： | 1 |
| 系列： | FemtoCharge™ |
| 位数： | 10 |
| 采样率（每秒）： | 250M |
| 数据接口： | 串行，SPI? |
| 转换器数目： | 2 |
| 功率耗散（最大）： | 438mW |
| 电压电源： | 单电源 |
| 工作温度： | -40°C ~ 85°C |
| 安装类型： | 表面贴装 |
| 封装/外壳： | 72-VFQFN 裸露焊盘 |
| 供应商设备封装： | 72-QFN（10x10） |
| 包装： | 托盘 |
| 输入数目和类型： | 2 个差分，单极 |
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17
FN6810.2
September 10, 2009
This relationship shows the SNR that would be achieved if
clock jitter were the only non-ideal factor. In reality,
achievable SNR is limited by internal factors such as
linearity, aperture jitter and thermal noise. Internal aperture
jitter is the uncertainty in the sampling instant shown in
Figure 1. The internal aperture jitter combines with the input
clock jitter in a root-sum-square fashion, since they are not
statistically correlated, and this determines the total jitter in
the system. The total jitter, combined with other noise
sources, then determines the achievable SNR.
Voltage Reference
A temperature compensated voltage reference provides the
reference charges used in the successive approximation
operations. The full-scale range of each A/D is proportional
to the reference voltage. The nominal value of the voltage
reference is 1.25V.
Digital Outputs
Output data is available as a parallel bus in LVDS-compatible
or CMOS modes. In either case, the data is presented in
double data rate (DDR) format with the A and B channel data
available on alternating clock edges. When CLKOUT is low
channel A data is output, while on the high phase channel B
relationships for LVDS and CMOS modes, respectively.
Additionally, the drive current for LVDS mode can be set to a
nominal 3mA or a power-saving 2mA. The lower current
setting can be used in designs where the receiver is in close
physical proximity to the ADC. The applicability of this setting
is dependent upon the PCB layout, therefore the user should
experiment to determine if performance degradation is
observed.
The output mode and LVDS drive current are selected via
the OUTMODE pin as shown in Table 2.
The output mode can also be controlled through the SPI
port, which overrides the OUTMODE pin setting. Details on
this are contained in “Serial Peripheral Interface” on
An external resistor creates the bias for the LVDS drivers. A
10k
Ω, 1% resistor must be connected from the RLVDS pin to
OVSS.
Over-Range Indicator
The over-range (OR) bit is asserted when the output code
reaches positive full-scale (e.g. 0xFFF in offset binary
mode). The output code does not wrap around during an
over-range condition. The OR bit is updated at the sample
rate.
Power Dissipation
The power dissipated by the KAD5610P is primarily
dependent on the sample rate and the output modes:
LVDS vs CMOS and DDR vs SDR. There is a static bias in
the analog supply, while the remaining power dissipation is
linearly related to the sample rate. The output supply
dissipation changes to a lesser degree in LVDS mode, but is
more strongly related to the clock frequency in CMOS mode.
Nap/Sleep
Portions of the device may be shut down to save power during
times when operation of the ADC is not required. Two power
saving modes are available: Nap, and Sleep. Nap mode
reduces power dissipation to less than 163mW and recovers
to normal operation in approximately 1s. Sleep mode
reduces power dissipation to less than 6mW but requires
approximately 1ms to recover from a sleep command.
Wake-up time from sleep mode is dependent on the state of
CSB; in a typical application CSB would be held high during
sleep, requiring a user to wait 150s max after CSB is
asserted (brought low) prior to writing ‘001x’ to SPI register
25. The device would be fully powered up, in normal mode
1ms after this command is written.
Wake-up from Sleep Mode Sequence (CSB high)
Pull CSB Low
Wait 150us
Write ‘001x’ to Register 25
Wait 1ms until ADC fully powered on
In an application where CSB was kept low in sleep mode, the
150s CSB setup time is not required as the SPI registers are
powered on when CSB is low, the chip power dissipation
FIGURE 31. SNR vs CLOCK JITTER
tj = 100ps
tj = 10ps
tj = 1ps
tj = 0.1ps
10 BITS
12 BITS
14 BITS
50
55
60
65
70
75
80
85
90
95
100
1M
10M
100M
1G
SNR
(dB)
INPUT FREQUENCY (Hz)
TABLE 2. OUTMODE PIN SETTINGS
OUTMODE PIN
MODE
AVSS
LVCMOS
Float
LVDS, 3mA
AVDD
LVDS, 2mA
KAD5610P
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相关代理商/技术参数 |
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| KAD5612P | 制造商:INTERSIL 制造商全称:Intersil Corporation 功能描述:Dual 12-Bit, 250/210/170/125MSPS A/D Converter |
| KAD5612P_09 | 制造商:INTERSIL 制造商全称:Intersil Corporation 功能描述:Dual 12-Bit, 250/210/170/125MSPS A/D Converter |
| KAD5612P_0909 | 制造商:INTERSIL 制造商全称:Intersil Corporation 功能描述:Dual 12-Bit, 250/210/170/125MSPS A/D Converter |
| KAD5612P-12Q72 | 功能描述:IC ADC 12BIT 125MSPS DUAL 72-QFN RoHS:是 类别:集成电路 (IC) >> 数据采集 - 模数转换器 系列:FemtoCharge™ 产品培训模块:Lead (SnPb) Finish for COTS Obsolescence Mitigation Program 标准包装:250 系列:- 位数:12 采样率（每秒）:1.8M 数据接口:并联 转换器数目:1 功率耗散（最大）:1.82W 电压电源:模拟和数字 工作温度:-40°C ~ 85°C 安装类型:表面贴装 封装/外壳:48-LQFP 供应商设备封装:48-LQFP（7x7） 包装:管件 输入数目和类型:2 个单端，单极 |
| KAD5612P-17Q72 | 功能描述:IC ADC 12BIT 170MSPS DUAL 72-QFN RoHS:是 类别:集成电路 (IC) >> 数据采集 - 模数转换器 系列:FemtoCharge™ 产品培训模块:Lead (SnPb) Finish for COTS Obsolescence Mitigation Program 标准包装:250 系列:- 位数:12 采样率（每秒）:1.8M 数据接口:并联 转换器数目:1 功率耗散（最大）:1.82W 电压电源:模拟和数字 工作温度:-40°C ~ 85°C 安装类型:表面贴装 封装/外壳:48-LQFP 供应商设备封装:48-LQFP（7x7） 包装:管件 输入数目和类型:2 个单端，单极 |
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