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参数资料
| 型号： | KIT18730EPEVBE |
| 厂商： | Freescale Semiconductor |
| 文件页数： | 8/35页 |
| 文件大小： | 0K |
| 描述： | KIT FOR MPC18730 PMIC |
| 标准包装： | 1 |
| 主要目的： | DC/DC，LDO 步降 |
| 输出及类型： | 5，非隔离 |
| 稳压器拓扑结构： | 降压 |
| 频率 - 开关： | 200kHz |
| 板类型： | 完全填充 |
| 已供物品： | 板，软件 |
| 已用 IC / 零件： | MPC18730 |
| 相关产品： | MPC18730EPR2-ND - IC PMIC PROGR 5-OUTPUTS 64-QFN MPC18730EP-ND - IC PMIC PROGR 5-OUTPUTS 64-QFN |
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ELECTRICAL CHARACTERISTICS
STATIC
Table 3. Static Electrical Characteristics (continued)
Characteristics noted under conditions VBATT = 1.2 V, VO1_SENSE = 2.4 V, VGATE= 6.0 V, f CLK = 176.4 kHz unless
otherwise noted. Typical values noted reflect the approximate parameter means at T A = 27°C under nominal conditions unless
otherwise noted.
Characteristic
Symbol
Min
Typ
Max
Unit
Switching Power Supply 2
V
VOUT2 Output Voltage (I o = 0~80 mA)
HG Output Voltage (11) (I source = 400 μ A)
(I sink = 400 μ A)
LG Output Voltage (11) (I source = 400 μ A)
(I sink = 400 μ A)
V OUT2
V DW2TH
V DW2TL
V DW2BH
V DW2BL
1.05
5.2
0
5.2
0
1.15
-
-
-
-
1.25
VGATE
0.3
VGATE
0.3
Series Pass Power Supply Circuit
SREG1 Control Voltage (I o = 5~60 mA) (12)
V SREG1
2.7
2.8
2.9
V
SREG1-Error AMP Input offset voltage
SR1OFST
-13.5
-
24.5
mV
SREG2 Control Voltage (I o = 6~80 mA) (12)
SREG2-Error AMP Input offset voltage (14)
SREG3 Control Voltage (I o = 5~60 mA) (12)
SREG3-Error AMP Input offset voltage (15)
SREG2G Output Voltage (16) (I source = 2.5 μ A)
V SREG2
SR2OFST
V SREG3
SR3OFST
SREG2GH
SREG2GL
2.7
-17
2.7
-11
5.0
0
2.8
-
2.8
-
-
-
2.9
17
2.9
23
VGATE
0.5
V
mV
V
mV
V
V
(I sink = 2.5 μ A)
Power Switch On Resistance
W
VOUT1 Circuit
VOUT2 Circuit
R VOUT1
R VOUT2
-
-
0.4
0.4
0.6
0.6
VGATE Power Supply Circuit
V
(I o = 0~6 mA)
(I o = 0~6 mA)
V GATE_00
V GATE_10
5.5
4.6
6.0
5.0
6.5
5.4
CH_PUMP Output Voltage (I source = 2.5 mA)
(I sink = 2.5 mA)
VGH Voltage (Certified value)
V O1_SENSE1LH
V O1_SENSE_1LL
V GH
VB x 0.85
0
-
-
-
-
VB
0.4
10.5
V_STDBY Output Voltage for Li_ion (I o = 300 μ A) (19)
V LVB
1.75
-
2.45
V
Notes
11. Connect a transistor with gate capacity of 200 pF or smaller to HG and LG
12. If a capacitor with capacitance of 22 μF is connected to SREGO, use a phase compensation capacitor between SREGO and SREGC
when the load is 5 mA (6 mA for SREG2) or lower. The output voltage values shown in the table assume that external resistance is
connected as follows:
SREGI1 = 3.0 V to 3.3 V, 65.14K ? between SREGO1 and SREGC1, 34.86K ? between SREGC1 and GND.
SREGI2 = 3.0 V to 3.3 V, 54.46K ? between SREGO2 and SREGC2, 45.54K ? between SREGC2 and GND.
SREGI3 = 3.0 V to 3.3 V, 73.84K ? between SREGO3 and SREGC3, 26.16K ? between SREGC3 and GND.
13. Calculated by the right formula for input offset: SR1OFST = (Vref x 0.77) - (SREGO1 ÷ (100k ÷ 34.86k))
14. Calculated by the right formula for input offset: SR2OFST = (Vref x 1) - (SREGO1 ÷ (100k ÷ 45.54k))
15. Calculated by the right formula for input offset: SR3OFST = (Vref x 0.58) - (SREGO1 ÷ (100k ÷ 26.16k))
16. Connect a transistor with gate capacity of 300 pF or smaller to REG2G.
17. When VGATESEL1 is Low and VGATESEL2 is Low, I/O = 3 mA or higher is certified by specification.
18. When VGATESEL1 is High and VGATESEL2 is Low, I/O = 3 mA or higher is certified by specification.
19. When HVB is 4.2 V and the load from V_STDBY is 0.5 μ A or higher.
18730
Analog Integrated Circuit Device Data
8
Freescale Semiconductor
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