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| 型号： | KIT33702DWBEVB |
| 厂商： | Freescale Semiconductor |
| 文件页数： | 13/39页 |
| 文件大小： | 0K |
| 描述： | KIT FEATURES THE MC34701 |
| 标准包装： | 1 |
| 主要目的： | DC/DC，LDO 步降 |
| 输出及类型： | 2，非隔离 |
| 输入电压： | 2.8 ~ 6V |
| 稳压器拓扑结构： | 降压 |
| 频率 - 开关： | 300kHz |
| 板类型： | 完全填充 |
| 已供物品： | 板，软件 |
| 已用 IC / 零件： | MC34702 |
| 相关产品： | MC34702EKR2CT-ND - IC POWER SUPPLY MCU 3A 32-SOIC MC34702EKR2TR-ND - IC POWER SUPPLY MCU 3A 32-SOIC MC34702EK-ND - IC POWER SUPPLY MCU 3A 32-SOIC |
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ELECTRICAL CHARACTERISTICS
DYNAMIC ELECTRICAL CHARACTERISTICS
Table 4. DYNAMIC ELECTRICAL CHARACTERISTICS (continued)
Characteristics noted under conditions -40°C ? T A ? 85 ? C unless otherwise noted. Input voltages VIN1 = VIN2 = 3.3V using
the typical application circuit (see Figures 33 ), unless otherwise noted.
Characteristic
Symbol
Min
Typ
Max
Unit
BOOST REGULATOR
Boost Regulator MOSFET Maximum ON Time (21)
Boost Regulator Control Loop Propagation Delay (21)
Boost Switching Node VBD Rise Time
t ON
t BST_PD
t B_RISE
–
–
24
50
–
–
? s
ns
ns
IBST = 20mA
Boost Switching Node VBD Fall Time (21)
IBST = 20mA
LINEAR REGULATOR (LDO)
t B_FALL
–
–
5.0
3.0
ns
Fault Condition Time-Out
Retry Timer Cycle
t FAULT
t RET
8.0
80
10
100
12
120
ms
ms
Reset Monitor ( RST )
Monitoring LFB Pin Delay
Monitoring INV Pin Delay
t D_RST_LFB
t D_RST_INV
12
12
–
–
28
28
? s
? s
SCA, SCL PIN, I 2 C BUS (STANDARD)
SCL Clock Frequency (21)
Bus Free Time Between a STOP and a START Condition (21)
Hold Time (Repeated) START Condition (After this period, the first clock
pulse is generated) (21)
Low Period of the SCL Clock (21)
High Period of the SCL Clock (21)
SDA Fall Time from VIH_MAX to VIL_MIN, Bus Capacitance 10pF to 400pF,
3.0mA Sink Current (21) , (23)
Setup Time for a Repeated START Condition (21)
Data Hold Time for I 2 C Bus Devices (21) , (22)
Data Setup Time (21)
Setup Time for STOP Condition (21)
Capacitive Load for Each Bus Line (21)
f SCL
t BUF
t HD-STA
t LOW
t HIGH
t F
t SU-STA
t HD-DAT
t SU-DA T
t SU-STO
CB
–
4.7
4.0
4.7
4.0
–
4.7
0.0
250
4.0
–
–
–
–
–
–
–
–
–
–
–
–
100
–
–
–
–
250
–
–
–
–
400
kHz
? s
? s
? s
? s
ns
? s
? s
ns
? s
pF
Notes
21. Design information only. This parameter is not production tested.
22. The device provides an internal hold time of at least 300ns for the SDA signal (refer to the V IH_MIN of the SCL signal) to bridge the
undefined region of the falling edge of SCL.
23. VIH = High level voltage on I2C bus and VIL = Low level voltage on I2C bus
34702
Analog Integrated Circuit Device Data ?
Freescale Semiconductor
13
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