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参数资料
| 型号： | KIT33702DWBEVB |
| 厂商： | Freescale Semiconductor |
| 文件页数： | 31/39页 |
| 文件大小： | 0K |
| 描述： | KIT FEATURES THE MC34701 |
| 标准包装： | 1 |
| 主要目的： | DC/DC，LDO 步降 |
| 输出及类型： | 2，非隔离 |
| 输入电压： | 2.8 ~ 6V |
| 稳压器拓扑结构： | 降压 |
| 频率 - 开关： | 300kHz |
| 板类型： | 完全填充 |
| 已供物品： | 板，软件 |
| 已用 IC / 零件： | MC34702 |
| 相关产品： | MC34702EKR2CT-ND - IC POWER SUPPLY MCU 3A 32-SOIC MC34702EKR2TR-ND - IC POWER SUPPLY MCU 3A 32-SOIC MC34702EK-ND - IC POWER SUPPLY MCU 3A 32-SOIC |
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TYPICAL APPLICATIONS
.
R2 = V Ref ? -----------------------------------------------------------------------------------------
? V O + I O ? R L ? – V Ref V O – V Ref
-------------------------------------------------------- + --------------------------
G ain
[dB]
20
fLC
R4 R1
1
0
fz(c)
f BW
fz(E SR) fp (FF)
Where V Ref is the buck regulator reference voltage ?
(V Ref = 0.8V typ.) at the INV pin, ?
V O is the selected output voltage, ?
I O is the output load current, ?
R L is the DC resistance of the inductor L.
-20
-40
-180
fp(c)
It is apparent that the buck regulator output voltage is
affected by the voltage drop caused by the inductor serial
resistance and the regulator output current. In those
applications which do not require precise output voltage,
setting the formula for calculating selected output voltage can
be simplified as follows:
R2 = V Ref ? ----------------------------------------------------------------
? V O – V Ref ? ? ---------------------------
Pha se
[Deg.]
1
? R1 + R4 ?
R1 ? R4
V LDO = V Ref ? ? ? ? ?
R U
-2 70
-3 60
? m
Linear Regulator Output Voltage
The output voltage of the linear regulator (LDO) can be set
by a simple resistor divider according to the following formula:
1 + -------
R L
1.0
10
100
10 00
10000
f z ? ESR ? = ----------------------------
Frequency [k Hz ]
Figure 30. Buck Control Loop Bode Plot
The frequency of the zero created by the ESR of the output
capacitor C O is calculated as:
1
2 ? C O ESR
Where C O is the value of the buck regulator output
capacitor, and ESR is the equivalent series resistance of the
output capacitor.
The frequency of the compensating network pole can be
calculated as follows:
Where V Ref is the linear regulator reference voltage ?
(V Ref = 0.8V typ.) at the LFB pin, ?
V LDO is the LDO selected output voltage, ?
R U is the “upper” resistor of the LDO resistor divider, ?
R L is the “lower” resistor of the LDO resistor divider.
Figure 31 describes the 34702 linear regulator circuit with
the resistor divider R U , R L setting the output voltage V LDO .
2.8 V to 6. 0 V Input
MC34701
VIN1
f p ? c ? = -------------------------------------------
2 ? C2 ---------------------------
1
R1R3
? R1 + R3 ?
The well designed and compensated buck regulator
should yield at least 45 deg. phase margin ? m of its overall
LDRV
CS
LDO
LFB
LCMP
RS
RU
RL
VLDO
CLDO
Selecting Buck Regulator Output Voltage
The 34702 buck regulator output voltage can be set by
selecting the right value of the resistors R1, R2 and R4, and
LDO
Compensation
Figure 31. 34702 Linear Regulator Circuit
page 30 for the component references):
34702
Analog Integrated Circuit Device Data ?
Freescale Semiconductor
31
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