参数资料
型号: KIT33879AEKEVBE
厂商: Freescale Semiconductor
文件页数: 10/23页
文件大小: 0K
描述: BOARD EVALUATION FOR MC33879
标准包装: 1
主要目的: 电源管理,高端和低端驱动器(内部 FET)
嵌入式:
已用 IC / 零件: MC33879
主要属性: 8 个输出硬件-可配置
次要属性: 16 位串行输入控制
已供物品: 板,CD
ELECTRICAL CHARACTERISTICS
DYNAMIC ELECTRICAL CHARACTERISTICS
DYNAMIC ELECTRICAL CHARACTERISTICS
Table 5. Dynamic Electrical Characteristics
Characteristics noted under conditions 3.1 V ? V DD ? 5.5 V, 5.5 V ? V PWR ? 18 V, - 40 ? C ? T C ? 125 ? C, unless otherwise
noted. Where applicable, typical values reflect the parameter’s approximate average value with V PWR = 13 V, T A = 25 ? C.
Characteristic
Symbol
Min
Typ
Max
Unit
POWER OUTPUT TIMING
Output Slew Rate Low Side Configuration (11)
t SR(RISE)
V/ ? s
R LOAD = 620 ??? C L = 200pF
Output Slew Rate Low Side Configuration (11)
R LOAD = 620 ??? C L = 200 pF
Output Rise Time High Side Configuration (11)
R LOAD = 620 ??? C L = 200 pF
Output Fall Time High Side Configuration (11)
R LOAD = 620 ??? C L = 200 pF
Output Turn ON Delay Time, High Side and Low Side Configuration (12)
Output Turn OFF Delay Time, High Side and Low Side Configuration (12)
t SR(FALL)
t SR(RISE)
t SR(FALL)
t DLY(ON)
t DLY(OFF)
0.1
0.1
0.1
0.1
1.0
1.0
0.5
0.5
0.3
0.3
15
30
1.0
1.0
1.0
1.0
50
100
V/ ? s
V/ ? s
V/ ? s
? s
? s
Output Fault Delay Time (13)
t FAULT
100
300
? s
Power-ON Reset Delay
t POR
? s
Delay Time Required from Rising Edge of EN and V DD to SPI Active
Low-State Duration on V DD or EN for Reset
V DD or EN ? 0.2 V
t RESET
100
100
μs
Notes
11. Output slew rate respectively measured across a 620 ? resistive load at 10 to 90 percent and 90 to 10 percent voltage points. ?
C L capacitor is connected from Drain or Source output to Ground.
12.
13.
Output turn ON and OFF delay time measured from 50 percent rising edge of CS to the beginning of the 10 and 90 percent transition
points.
Duration of fault before fault bit is set. Duration between access times must be greater than 300 ? s to read faults.
33879
Analog Integrated Circuit Device Data ?
10
Freescale Semiconductor
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