参数资料
型号: KIT33989DWEVB
厂商: Freescale Semiconductor
文件页数: 29/72页
文件大小: 0K
描述: KIT EVAL 33989DW HS SBC
标准包装: 1
主要目的: 接口,CAN 控制器
嵌入式: 是,MCU,8 位
已用 IC / 零件: MC33989
主要属性: CAN 2.0 系统基础芯片(SBC),SPI 接口,2 低压降稳压器
次要属性: 故障检测,睡眠和待机模式
已供物品: 板,CD
相关产品: MC33989DWR2CT-ND - IC SYSTEM BASE W/CAN 28-SOIC
MC33989DWR2TR-ND - IC SYSTEM BASE W/CAN 28-SOIC
MC33989DW-ND - IC SYSTEM BASE W/CAN 28-SOIC
Analog Integrated Circuit Device Data
Freescale Semiconductor
35
33989
FUNCTIONAL DEVICE OPERATION
LOGIC COMMANDS AND REGISTERS
Error bits are latched in the CAN registers. Bit (1) CUR is set to 1 when the CAN interface is programmed into CAN NORMAL
for the first time after V2 turn ON. To clear the CUR bit, follow this procedure:
Turn V2 ON (SBC in Normal mode and V2 above V2 threshold) the CAN interface must be set into CAN Sleep
Return to CAN NORMAL
Input/Output Control Register (IOR)
Table 19 provides data about HS1 control in Normal and Standby modes, while Table 20 provides control bit data.
When HS1 is turned OFF due to an over temperature condition, it can be turned ON again by setting the appropriate control
bit to 1. Error bits are latched in the Input/Output Registers (IOR). See Table 21.
1
0
CAN Normal, Slew Rate 3
x
1
CAN Sleep and CAN Wake-up Disable
x
0
1
CAN Sleep and CAN Wake-up Enable
Table 18. CAN Status Bits
Status Bits
Description
CANWU
CAN Wake-up Occurred
TXF
Permanent Dominant TX
CUR(1)
CAN Transceiver in Current Limitation
THERM
CAN Transceiver in Thermal Shutdown
Table 19. IOR Register
IOR
D3
D2
D1
D0
$011B
W
HS1ON
R
V2LOW
HS1OT
VSUPLOW
DEBUG
Reset Value
0
Reset Condition
POR
Table 20. IOR Control Bits
HS1ON
HS1 State
0
HS1 OFF, in Normal and Standby Modes
1
HS1 ON, in Normal and Standby Modes
Table 21. IOR Status Bits
Status Bit
Description
V2LOW
V2 Below 4.0 V
HS1OT
High Side 1 Overtemperature
VSUPLOW
VSUP Below 6.1 V
DEBUG
If Set, SBC Accepts Command to go to Debug Modes (No WD)
Table 17. CAN High Speed Transceiver Modes
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