参数资料
型号: KIT33989DWEVB
厂商: Freescale Semiconductor
文件页数: 42/72页
文件大小: 0K
描述: KIT EVAL 33989DW HS SBC
标准包装: 1
主要目的: 接口,CAN 控制器
嵌入式: 是,MCU,8 位
已用 IC / 零件: MC33989
主要属性: CAN 2.0 系统基础芯片(SBC),SPI 接口,2 低压降稳压器
次要属性: 故障检测,睡眠和待机模式
已供物品: 板,CD
相关产品: MC33989DWR2CT-ND - IC SYSTEM BASE W/CAN 28-SOIC
MC33989DWR2TR-ND - IC SYSTEM BASE W/CAN 28-SOIC
MC33989DW-ND - IC SYSTEM BASE W/CAN 28-SOIC
Analog Integrated Circuit Device Data
Freescale Semiconductor
47
33989
TYPICAL APPLICATIONS
SUPPLEMENTAL APPLICATION NOTES
LX Wakes up SBC from Sleep Mode
Below is the case where the SBC is in sleep mode and is awaked by LX positive edge.
Figure 26. SBC in Sleep Mode
T1 (LX high level to VDD1 turn on): typ 100 s.
T2: VDD1 rising time is dependent on the capacitor and the load connected to VDD1. It can be approximated by the capacitor
charging time with the regulator output current limitation: T2 = (C x U)/I. With C = 100 mF, IDD1 = 200 mA min., U = 5.0 V
so T2 = 2.5 ms).
T3 (VDD1>RST-TH (4.6 V by default) to reset high): parameter Rest dur: 4.0 ms max.
The total time is 6.6 ms in this example.
CAN Wake-up
The following case describes the signal for CAN wake-up. Refer to page 53 for more details on CAN wake-up signals and the
TCAN analysis.
Figure 27. CAN Wake-up
T1(third valid CAN dominant pulse to VDD1 turn on): typ 80 s.
T2 and T3 identical to page 42 above
The total time is 6.58 ms in this example.
LX with Cyclic Sense
The case below is a description of the wake-up by LX input associated with the cyclic sense function.
Figure 28. Wake-up by LX Input
LX
VDD1
RST
t1
t3
t2
CAN
VDD1
RESET
t1
t2
t3
tCAN
RST
LX
VDD1
RESET
t2
t1
HS1
t3
t4
RST
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