参数资料
型号: KMPC8314ECVRAGDA
厂商: Freescale Semiconductor
文件页数: 97/101页
文件大小: 0K
描述: IC MPU POWERQUICC II 620-PBGA
标准包装: 2
系列: MPC83xx
处理器类型: 32-位 MPC83xx PowerQUICC II Pro
速度: 400MHz
电压: 1V
安装类型: 表面贴装
封装/外壳: 620-BBGA 裸露焊盘
供应商设备封装: 620-PBGA(29x29)
包装: 托盘
MPC8314E PowerQUICC II Pro Processor Hardware Specifications, Rev. 2
Freescale Semiconductor
95
System Design Information
24.3.1
Experimental Determination of the Junction Temperature with a
Heat Sink
When heat sink is used, the junction temperature is determined from a thermocouple inserted at the
interface between the case of the package and the interface material. A clearance slot or hole is normally
required in the heat sink. Minimizing the size of the clearance is important to minimize the change in
thermal performance caused by removing part of the thermal interface to the heat sink temperature and
then back calculate the case temperature using a separate measurement of the thermal resistance of the
interface. From this case temperature, the junction temperature is determined from the junction to case
thermal resistance.
TJ = TC + (RJC x PD)
Where
TC is the case temperature of the package
RJC is the junction-to-case thermal resistance
PD is the power dissipation
25 System Design Information
This section provides electrical and thermal design recommendations for successful application of the
MPC8314E.
25.1
System Clocking
The MPC8314E includes two PLLs.
1. The platform PLL (AVDD2) generates the platform clock from the externally supplied
SYS_CLK_IN input. The frequency ratio between the platform and SYS_CLK_IN is selected
using the platform PLL ratio configuration bits as described in Section 23.1, “System PLL
2. The e300 Core PLL (AVDD1) generates the core clock as a slave to the platform clock. The
frequency ratio between the e300 core clock and the platform clock is selected using the e300
PLL ratio configuration bits as described in Section 23.2, “Core PLL Configuration.”
25.2
PLL Power Supply Filtering
Each of the PLLs listed above is provided with power through independent power supply pins
(AVDD1,AVDD2 respectively). The AVDD level should always be equivalent to VDD, and preferably
these voltages are derived directly from VDD through a low frequency filter scheme such as the following.
There are a number of ways to reliably provide power to the PLLs, but the recommended solution is to
provide independent filter circuits as illustrated in Figure 61, one to each of the AVDD pins. By providing
independent filters to each PLL the opportunity to cause noise injection from one PLL to the other is
reduced.
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